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Where There’s a Bridge, There’s a Way

COLLIN MCCRACKEN & PAUL ROSENFIELD

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Embedded designers in all market segments have become enamored with the new ultra-low-power Atom and Nano processors from Intel and VIA, respectively. For years, hardware engineers have been asking processor manufacturers to reduce the power envelope of their notebook/mobile PC processors and chipsets for the embedded market. After all, 100W-plus desktop CPU chips outstripped embedded market requirements nearly 10 years ago. Even modern mobile-focused CPUs such as Eden, Celeron and Geode rarely met the thermal characteristics required for a small form factor, fanless CPU board to operate in a small or sealed enclosure. Newer multicore designs were not a step in the right direction. If the software engineers aren’t fully utilizing one core, why add the power requirements of a second core?

Atom and Nano, however, have hit the small form factor sweet spot. For years, 486 and Pentium MMX processors reigned in embedded designs, giving way to Eden, Celeron and Geode. The “heirs apparent” are clear, or are they?

While desktop PCs and, to a certain extent, laptop/notebook/sub-notebook PCs are largely cookie-cutter designs, most embedded applications are unique. I/O requirements, processing throughput, size, thermal design, MTBF and operating systems vary widely. What about solid-state mass storage (SSDs)? Serial ports? Expansion buses such as ISA (shudder) and PCI? The reality is that legacy I/O and buses are still in demand. Reconciling these requirements with the new legacy-free chipsets supporting Atom and Nano is the challenge.

Designers now get to add the features they need, a la carte style. To add the ISA bus, there are several options. Bridging from the LPC bus involves a low-cost device from several silicon vendors, with modest feature sacrifices such as DMA, address space and single-cycle 16-bit transfers. To preserve these features, a PCI-to-ISA bridge can be used–at a higher cost. Of course, the BIOS must initialize the bridge selected. Unfortunately, the parallel 32-bit/33 MHz PCI bus is not supported on some low-power chipsets.

For applications requiring legacy PC I/O-like serial ports, parallel port, or PS/2 keyboard or mouse, one straightforward approach is to add a super I/O IC to the LPC bus. Some chip vendors offer serial port ICs that attach to the PCI bus. Many applications require general-purpose digital I/O. Southbridge ICs usually have a few spare GPIO pins, some are used internally, and few are brought to an I/O connector. Interrupts on change of state are not available. When using a computer-on-module (COM) rather than a single board computer (SBC), it is critical to confirm that GPIO pins are defined on the carrier board interface, and that the module under consideration connects these signals.

Where PATA/IDE devices are used, be they rotating disk drives or solid state storage, there is good news for now anyway. Nearly all low-power chipsets still have this interface. Several new SSD standards and form factors will be available in 2009 using USB, SATA, or other interfaces to enable a smooth transition before PATA goes away entirely. At some point, a stand-alone IDE controller will be required to continue to support those devices, much like the original way disk controllers were designed in. This again, however, leads us back to a PCI bus requirement.

Moving up to higher speed bus interfaces, PCI Express has already begun to overtake PCI in the large form factor arena (motherboards and blades for card cages). The small form factor market is now rushing headlong into this space as well. Many alternatives are available for off-the-shelf boards and custom designs. One challenge is that PCI is being replaced by PCI Express x1 (“by one”) lanes. Parallel PCI can be obtained by bridging from PCI Express. While software engineers celebrate the transparency of this bridge, they will be working overtime to help the firmware engineer get the legacy I/O to work. A final gotcha here focuses on bandwidth, of all things. PCI supports 4 devices natively, and up to 32 devices with PCI to PCI bridging. Cramming 4 PCI devices onto a single PCI Express x1 lane does not provide for the rip-roaring transmission of data. What to do about the limited PCI Express lanes becomes the topic of a future column.

The challenges are compounded when several of the aforementioned bridges and super I/O devices are used together. Getting these neat low-power chips to work in your application can become a bit of a chore, considering how much has to be added to make them fit your unique requirements! Comments about this topic can be sent to sf3@rtcgroup.com.