The LPC Bus
LPC Bus-Legacy Lives On
With all the advances in processor and I/O technology, what has become of the venerable I/O devices that are still so useful for a wide range of applications? The preservation of the LPC bus offers a low-cost and straightforward way to continue using these legacy devices.
ROBERT BURCKLE, WINSYSTEMS AND JEFF MUNCH, ADLINK
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Legacy buses and I/O appear to be on the chopping block. Large pin count parallel communications buses are being replaced by faster serial architectures. Examples include Serial ATA (SATA) replacing IDE/Parallel ATA (PATA) and PCI Express replacing parallel PCI. After the ISA bus was phased out of the modern x86 chipsets, the major semiconductor companies realized that users were critically concerned about how to attach relatively low-speed serial and parallel devices. Typically these devices would be a super-I/O device or a boot ROM.
Electronics system manufacturers request the continued availability of simple, low-cost I/O that would give them COM ports, relay interfaces, and modest bandwidth A/D and D/A converters. Hanging multiple bus bridges, translators and FPGAs off of the PCI bus or a PCI Express x1 lane to get to low-speed I/O is cumbersome, adding unnecessary risk, cost, power consumption, design/debug time, software development and board space usage. The best path forward is the Low Pin Count (LPC) bus. The challenge to designers is how to move their legacy I/O forward, and with what board/bus architecture.
The LPC bus was defined by Intel in 1998. Its purpose is to take over for the 8/16-bit ISA bus where legacy is needed while greatly reducing pins (balls) and board space for traces. First and foremost, the goal was to reduce the cost of attaching firmware (the BIOS), and secondly to provide a continued path to legacy peripherals and expansion slots. LPC is a 4-bit wide bus with far fewer lines than ISA, but with a faster multiplexed 33 MHz address and data speed to compensate. It even supports serialized interrupts and DMA. In most cases, few software modifications are needed to migrate to LPC from ISA since the peripheral side is simple and low speed. Furthermore, the LPC bus is able to support wake-up and other power-state transitions, which the ISA bus cannot support.
LPC requires a minimum of seven signals. LAD [3:0] comprise the four data lines, and the other three are control signals. LFRAME# indicates the start of a new cycle or termination of a broken cycle, LRESET# provides the same type of function as the PCI reset signal, and LCLK is a 33 MHz clock. Optionally there are sideband signals that convey power management and interrupts. For example, LDRQ# is defined to support DMA operation while SERIRQ allows peripherals to generate an interrupt if the host does not have ISA-based IRQ lines as interrupt inputs. Optional signals may or may not be on particular hosts or peripherals.
The latest generation of microprocessor chips from Intel (the Atom family) and from VIA (Nano) show continued retention of legacy software support and LPC bus for low-speed peripherals. Even though PCI Express and USB2.0 catch a lot of attention, LPC remains the unsung hero for boot ROM and legacy I/O devices.
For designers who need an LPC solution, off-the-shelf ICs exist in the market. Alternatively, PLDs or FPGAs can be designed. SMSC (www.smsc.com) is one example of a commercial chip manufacturer with off-the-shelf solutions for non-PC and embedded computing platforms using LPC, USB and other solutions. SMSC provides straight UART ICs (4-port, 6-port, etc.) as well as chips with the full complement of legacy I/O (UARTs, parallel port/LPT, PS/2 keyboard & mouse). Other vendors include Winbond and Fintek.
Lattice Semiconductor is an example of a programmable IC manufacturer whose devices can be targeted for custom designs. Lattice offers an LPC Bus Controller Reference Design that implements an LPC host and an LPC peripheral that support the seven required LPC control signals. The design is implemented in Verilog, and Lattice design tools are used for synthesis, place and route, and simulation. The design can be targeted to multiple Lattice device families, and its small size makes it portable across different FPGA/CPLD architectures. Verilog source code is included.
Although LPC was intended as an onboard inter-chip bus, new and recent embedded form factors bring LPC “off-road.” The form factors fall into the usual two classifications: Stackable and Computer-on-Module (COM).
In the stackable architecture, the Small Form Factor SIG (SFF-SIG, www.sff-sig.org) introduced a standardized way to bring LPC vertically off the host SBC to a mezzanine expansion I/O card. The interface, called SUMIT, includes a mix of high-speed and other low-speed buses and signals. The first SBC form factor available with SUMIT is called Pico-ITXe (Figure 1). The SUMIT-AB connector pair is located along the front edge.
Rather than creating a custom single board computer, an off-the-shelf Pico-ITXe SBC can be expanded with a Pico-I/O card to add whatever I/O is needed by a particular application. This approach reduces time, resources and risk compared to full custom designs. Figure 2 shows a complete, off-the-shelf industrial I/O solution based upon tiny building blocks.
WinSystems chose the Lattice approach for their first Pico-I/O-compatible product. The PCO-UIO48-G is a 48-line, digital input/output module that will operate from -40° to +85°C. The major feature of this card is its ability to monitor the first 24 lines for both rising and falling digital edge transitions, latch them, and then interrupt the host processor notifying that a change-of-input status has occurred. This is an efficient way of signaling a Pico-ITXe single board computer (SBC) of real-time events without the burden of polling the digital I/O points.
WinSystems uses a Lattice FPGA device programmed to support the various input/output and interrupt configurations. It supports 48 digital I/O lines addressed through six contiguous registers. A 6-bit write mask register allows the user to disable writes on a byte basis to configure the group as a “read only” port. Each I/O line is individually programmable for input, output, or output with read back operation. The input lines are connected so that the current status of its output port can be read from the corresponding input port (read back). If the port is used as input only, then the corresponding output port bit must be cleared. Each output channel is latched and has an open collector driver with a pull-up resistor. The I/O structure of the FPGA works with 3.3V but is +5V tolerant for maximum system flexibility.
Requiring all new I/O to be attached to either PCI Express or USB is unwise. It is like trying to get a simple drink of water from a firehose. LPC provides a proven, easy way to attach simple devices with reasonably deterministic real-time response, without requiring costly hardware and software overhead plus development time and money.
The very first SUMIT-based SBC on the market in the 90 x 96 mm ISM (Industry Standard Module) form factor is shown in Figure 3. ISM is the term for the pure board outline compatible with PC/104 enclosures, but without pre-supposing any buses like the PC/104 (ISA) bus. Adlink’s CoreModule 730 uses the Atom processor at 1.1 or 1.6 GHz for the lowest power implementation possible with all Intel ICs—only 5 watts. Best of all, this solution does not require a custom carrier board, and is more economical than pre-integrated two-board PC/104 solutions. For modest I/O requirements including basic control applications, this approach is tiny, rugged and easy to cool even in sealed enclosures.
Stackable I/O cards like Adlink’s MiniModule SIO plug into the SUMIT interface and connect the LPC bus to an SMSC legacy super I/O device on the I/O module. Stackable LPC bus is also available on larger size SBC form factors. To download the SUMIT specification, visit www.sff-sig.org.
PICMG’s COM.0 specification primarily uses LPC for port 80 debug support. Connecting the LPC bus to legacy super I/O’s might require the COM Express modules to have BIOS initialization support for the custom carrier board’s device a priori. That said, a number of the COM vendors offer carrier reference designs with an LPC header or with an onboard super I/O device that is initialized by the module’s BIOS.
Reference design carriers often take the form of large ATX-style motherboards, since the size doesn’t really matter for a reference design. There are prototyping advantages to fitting into an ATX tower chassis. System OEMs wishing to add LPC devices to their carriers can follow the examples of the reference carrier boards.
Most COMs from major suppliers contain a BIOS that can initialize an LPC super I/O device. Typically the COM vendor must choose in advance what device to support. The Express-MV product shown in Figure 4 initializes the Winbond 83627 IC, so carriers designed for Express-MV that want to use legacy I/O need to select the Winbond device. For SMSC or other super I/O device, a custom BIOS would be needed. Figure 5 shows an Extreme Rugged -40° to +85°C module that is a rare COM with a larger BIOS firmware in order to support two super I/O devices (SMSC, Winbond, or both) on the carrier board. The BIOS support gives more flexibility to carrier designers to choose between two of the most popular devices without needing a custom BIOS.
Finally, Figure 6 shows an unusual carrier board reference design that is 5.75 x 8” (EBX size), much smaller than ATX size, and is much more than just a reference design. The COM-EBX baseboard contains a secondary LPC BIOS socket as an alternative to the module’s BIOS, as well as an SMSC super I/O device for legacy I/O support. COM-EBX is even deployable in volumes as a rare -40° to +85°C Extreme Rugged carrier for COM 840.
Whether a stackable, COM, or even custom SBC architecture is chosen, the LPC bus gives legacy additional longevity. Clearly, legacy I/O didn’t become obsolete when it disappeared from most new chipsets. LPC offers a simpler, software-transparent, less expensive and lower power way to attach legacy peripherals to embedded systems than using high-speed differential pair topologies like USB, Ethernet and PCI Express. Legacy I/O continues to live on in embedded systems.
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