RTC Magazine

With each successive generation of the industry standard PCI Express (PCIe) interconnect, the technology has been able to double its bandwidth, while at the same time adding features to improve system robustness. Designers now using PCIe Gen 1 and Gen 2 technology can look forward to another significant performance jump—to an incredibly fast eight gigabits per second (Gbits/s) per lane and 128 Gbit/s in designs using x16 port widths—along with a number of optimizations for enhanced signaling and data integrity, while maintaining full compatibility with the PCIe protocol stack and interoperability with components that support only the lower speed.

As with PCIe Gen 2, the earliest adopters of Gen 3 technology will be in the graphics space, where there is an insatiable demand for speed. Additionally, we expect to see this type of bandwidth used in fabrics for high-performance compute platforms and RAID storage systems, video capture and broadcast distribution systems where the additional bandwidth will allow the interconnect to outpace the existing interconnect technologies (Figure 1). Additionally, the improvements in link integrity and equalization will extend the adoption of PCIe in cabling and backplanes, with significant opportunities for both reducing cost and power while increasing performance.

PCIe Gen 3 Doubles Bandwidth

PCIe Gen 3 doubles the bandwidth of the interconnect without doubling the encoded bit rate. By comparison, the PCIe Gen 2 bit rate is 5 GigaTransitions per second (GT/s), and its 8b/10b encoding scheme provides an interconnect bandwidth of 4 Gbit/s per lane. A simple approach to doubling the PCIe interconnect bandwidth would have been to maintain the 8b/10b coding and then double the bit rate to 10GT/s, providing Gen 3 with an 8 Gbit/s per lane interconnect bandwidth. However, after extensive analysis, the PCI SIG determined that the overhead associated with the 8b/10b code could be eliminated by using scrambling to obtain DC balance, together with a 128,130 encoding scheme. This results in a useful bandwidth per lane of 8Gbits/s, less ~1.5% due to coding, with an encoded bit rate of only 8 GT/s. This lower bit rate results in lower power consumption, less silicon area and better signal integrity than a standard that would require a full 10 GT/s rate. This of course translates into reduced cost and improved efficiency. Table 1 shows the migration of PCIe bandwidth performance from Gen 1 through Gen 3.

What’s the trade-off? Since there’s no such thing as a free lunch, there must be some impact to the move from 8b/10b to a scrambling coding scheme. The 8b/10b encoding maps each byte of data into one 10-bit character. While using 8b/10b encoding does increase the bit rate, the benefit is that it guarantees a deterministic DC wander. This allows for the AC-coupling of the physical lane signals, and thereby relaxes the requirements for data recovery, simplifying the receiver design of the PHY.

The Gen 3 coding uses scrambling, rather than 8b/10b encoding. Scrambling is a technique by which a known polynomial is applied to the data stream in a feedback topology. Since the polynomial is known, the data is recovered by applying the inverse polynomial. The drawback at the PHY layer is that DC wander can be introduced, requiring the receiver to either correct for DC wander or be able to tolerate the accompanying margin degradation associated with DC wander.

There is also a drawback at the protocol layer: whereas the 8b/10b scheme provides out-of-band control characters that can identify the beginning and the end of a packet; with scrambling these characters do not exist. This will require additional circuitry in the transmitters and receivers, such as packet length counters, to delineate the beginning and ending of each packet. This additional circuitry has the potential to increase cost, power and complexity, but again, there’s no free lunch. Studies show that the trade-offs are worth it, since the reduced bit rate of the scrambling technique allows for the entire PHY to operate at a 20 percent lower frequency and still achieve the same link bandwidth.