RTC Magazine

As embedded applications become more responsive to their environments, the number of peripherals needed to capture and process data is exploding. It is commonplace for microcontrollers to have ADCs, DACs, PWMs, multiple timer/counters and numerous TWI, SPI, CAN, USB and USART interfaces for communications. More peripherals mean more cycle-intensive interrupts, and the amount of data that must be moved between the memories and the peripherals grows exponentially.

Generally, the CPU is in charge of processing interrupts and moving data. In some applications the CPU may spend most of its cycles on these activities. For example, managing two simultaneous inter-peripheral communications and a single 64 Mbit/s data transfer would require 200 CPU MIPS and consume 240 mA due to the extensive context switching and interrupt usage involved. In order to meet the extra computational load, the CPU clock may have to be increased, with a linear increase in power consumption. In extreme cases, the design must be migrated from an 8-/16-bit to a 32-bit device, just to keep up.

Frequently, a signal on a peripheral does not in itself require the CPU to do anything except let another peripheral know it needs to do something. Unfortunately, liaising between two peripherals requires cycle-intensive interrupt processing. For example, in a motor control application, overheating is prevented by constantly measuring the current on the motor and toggling an analog comparator when an over-current situation signals that the motor has stalled. The CPU is interrupted and shuts down the pulse width modulator (PWM) output for the motor driver. This process can require tens of cycles plus another 20-100 cycles to restore the context. The microcontroller is not really doing anything that requires its processing capabilities. It is basically just passing a message from an analog comparator to a PWM output. The cycles are basically wasted.

Other cycle wasters include the use of timer/counters to time other peripherals such as ADCs and DACs. In these situations, an interrupt is generated to start every conversion. At a sample rate of just a few kHz, these timer/counter interrupts consume over 1 MIPS—about 8% of a 12 MIPS MCU’s capacity.

If these peripherals could communicate with each other directly without interrupting the CPU, millions of cycles could easily be saved each second. One reason why 8-bit applications outgrow 8-bit microcontrollers is that, as applications become more data-intensive and interrupt-driven, most of the MCU’s MIPS are wasted on these activities. Transferring data between the peripherals and memories further increases the load on the MCU. A 350 Kbit/s data transfer requires between 22 and 25 CPU MIPS.

One solution to this problem is to use a low-power 8/16-bit single-cycle RISC MCU with an 8-channel event system and DMAs that off-load these functions from the CPU. This microcontroller architecture allows the simultaneous execution of up to 8 inter-peripheral events, plus up to four 64 Mbit/s data transfers, while consuming a total of less than 10 mA. Since the event system and DMA allow the peripherals to communicate with each other autonomously, no CPU clock cycles or interrupts are required. The CPU can be put into sleep mode.

The event system routes peripheral signals through a dedicated network outside the CPU data bus and DMA controller. The benefit of this is predictable and latency-free inter-peripheral signal communication that reduces CPU time and frees up interrupt resources. The event system enables a change of state in one peripheral to automatically trigger actions in other peripherals. In the motor control example cited earlier, an analog comparator, timer/counter, I/O pin or ADC in the microcontroller can directly shut off the PWM for the motor drive within two cycles of an over-current situation, offering better protection for the motor, while using zero interrupts and zero CPU cycles (Figure 1).

Peripheral events that can trigger the event system include timer/counter compare match or overflow, analog comparator toggle, pin change, ADC complete or compare and real-time counter overflow. Events that can be triggered in other peripherals include ADC or DAC conversion, input capture to time stamp communication or ADC measurements, external frequency or pulse-width measurements, clocking of timer/counters, starting a DMA transaction or changing a pin output.