VPX has great promise. VPX leverages the Eurocard 3U and 6U form factors. MIL/Aero system integrators have used these types of modules, like VME and CompactPCI boards, in rugged embedded applications for many years. Similarly, the VPX module has provisions for PMC and/or XMC I/O mezzanines, but adds a P0 connector for power, reference clocks, geographical pin assignments, JTAG, non-volatile write protection, system reset and out-of-band management. VPX also specifies a new connector to support the latest serial fabric technology, special alignment posts, card keying, safety grounds and 160 (3U) or 480 (6U) signal connections. Adding VPX-REDI (VITA 48) defines module ESD covers, larger horizontal pitch widths to accommodate the latest high-performance silicon, and every type of cooling imaginable.

The key differentiator of the VPX form factor is the new connector, the Multi-Gig RT2 (Figure 1). This wafer-based connector provides special ESD ground planes, single-ended connections for bused-type signals, and differential paired (diff-pair) traces specifically designed to route high-speed SerDes type communications between modules on a backplane. Tyco has designed the Multi-Gig RT2 connector to support greater than 5 GHz signal speeds, which accommodates USB 2.0, PCIe 2.0, sRIO 2.1, 10GigE, FPGA SERDES and other high-speed serial fabrics.

Other VITA standards like VITA 60 and 63 have specified compatible connectors that could replace the Multi-Gig connector for even more vibration and shock intense applications, as well as connectors for special signal capability like optical (VITA 66) and radio frequency (VITA 67). VPX, VPX-REDI and all of the other related VITA specifications should support current and future processing and data-communication technologies for the MIL/Aero market.

VPX - The Issue

Regardless of the connector strategy, the problem with serial fabrics is that they are point-to-point. Therefore, when defining the backplane for two or more VPX modules with serial fabrics, the designer must connect each differential pair, or diff-pair, to exactly one other module’s diff-pair. Most serial fabrics are duplex communications such that one lane requires four connection pins (one module’s diff-pair transmits to another modules diff-pair receive port and vice versa). 

If there are more VPX modules in the system, then more connection pins are necessary for data communications.  Designers can aggregate the diff-pairs together for larger data bandwidth, but this takes even more connections. Even with 480 (for 6U) or 160 (for 3U) pins available to the VPX module designer, high-bandwidth serial communications with many modules to connect can quickly utilize most of the available pins, leaving very few for specialized module I/O (Figure 2). 

Open VPX

VPX and VPX-REDI define a module’s dimensions, connectors, power, utility connections and fabric protocols; they do not define how to use these specifications at the system level. Depending on fabric choice, bandwidth need, module capability and I/O selections, there are many ways to create a system. To address this issue, a group of companies created OpenVPX.

OpenVPX is a working group designed to accelerate the ability for customers to buy interoperable VPX development systems and modules from independent vendors. Most VITA members are part of this working group, which will release the OpenVPX specification for VSO ratification into VITA 65 by the end of 2009. It is the hope that VPX vendors will refer to new VPX modules and systems as OpenVPX to communicate the new interoperable, easy-to-develop and ready for the future Eurocard standard.

Everything Is in the Taxonomy

OpenVPX defines a pipe as connections made up of diff-pairs. For example, an Ultra-Thin Pipe (UTP) is two diff-pairs or four connections on a Multi-Gig connector. A Thin-Pipe (TP) is four diff-pairs, and a Fat-Pipe (FP) is eight diff-pairs.  Fat-Pipe grouping expands to Double Fat Pipe (DFP), Quad Fat Pipe (QFP) and Octal Fat Pipe (OFP) to describe the largest bandwidth plane needed (Table 1). The plane is the type of communication that uses pipes. OpenVPX defines planes as interoperable data connections between modules. For example, if a plane has 1.0 Generation PCIe fabric on an UTP, this would equal one lane (x1) of PCIe at 2.5 Gigabits per second duplex.  Finally, profiles are classes of modules, slots, backplanes and chassis, which define a system.