TECHNOLOGY IN CONTEXT
New Directions for Mezzanines
New Generation of M-Modules and PMCs Saves Development Time and Money
FPGA technology built into a flexible submodule that can fit onto popular mezzanine standards can speed time-to-solution for a variety of specialized I/O demands.
BARBARA SCHMITZ, MEN MIKRO ELEKTRONIK
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Industrial embedded applications with small or medium volumes need tailor-made control solutions that can be implemented as much as possible on the basis of standard components. The development of any mezzanine concept is focused on flexibility to achieve low design costs and a short time-to-market. This is true for the various system-on-module (SoM) families, which accommodate the CPU functionality on a plug-on module, as well as for mezzanine standards like PMC or M-Module, which typically place I/O functions on the plug-on module.
Despite mezzanine technologies, the differences between I/O requirements may be huge, so it is not always possible to meet demands through available standards. Cost-effectively mitigating development costs and production time has historically been a challenge for embedded designers.
One approach to optimizing I/O flexibility is the Universal Submodule (USM) that uses FPGA technology, which has become inexpensive for even simple I/O demands. The functionality of the mezzanine module is defined solely through the combination of IP cores in the FPGA. In addition, FPGAs—and therefore any of the installed functions—are easily upgraded and readily available, which means they are unaffected by obsolete components, and are qualified for the extended temperature range of -40° to +85°C. USM was designed in such a way that it can be used for both PMC modules and M-Modules, the two most popular mezzanine standards.
PMC derivates, such as XMC, and the option of conduction cooling for M-Modules and PMC modules were also taken into account during the concept’s development. These mezzanine types are typically used in 19-inch systems such as CompactPCI or VME but also on stand-alone platforms. A 6U board can accommodate up to four M-Modules or three PMCs, while a 3U board can carry one PMC or up to two M-Modules.
Looking Forward with FPGA Technology
The Universal Submodule concept gives life to a new generation of M-Modules and PMCs that implement the desired functionality entirely in the shape of an IP core or a number of cores inside the FPGA. The FPGA itself is located on the “basic” PMC or “basic” M-Module and is a Cyclone II component from Altera in different versions starting at a size of 18,752 logic elements (which corresponds to about 225,000 gates). The hardware configuration of the FPGA is loaded during the boot phase from an external, 2 Mbyte NOR Flash using a CPLD, and is serially transmitted to the FPGA (Figure 1).
The USM concept standardizes many of the complex components to limit development costs and time to market.
The flash memory contains the source code for a minimum configuration of the FPGA over a PCI bus connection. When the Cyclone II is programmed with the basic configuration, the hardware configuration itself can be loaded into the second area of flash memory via the PCI bus. The Nios soft processor, also implemented in the FPGA, can provide local intelligence where needed. Accordingly, up to 32 Mbytes of DDR2 SDRAM can be assembled on the basic “main module.”
The cores inside the FPGA may have totally different functions from computer I/O, such as graphics, Ethernet and UARTs, to mobile or industrial communication with fieldbus connection, including CAN bus, Profibus, Industrial Ethernet, IBIS and MVB, up to typical industrial functions such as digital/analog process I/O, motor control and SSI. The configuration of a USM-based M-Module or PMC can be changed at any time through the implementation of different IP cores. Except for their FPGA contents, the main M-Modules or main PMCs have a fixed hardware setup. On the front, the user-defined I/O signals from the FPGA are led to a 50-pin SCSI 2 connector, chosen because it fits on the mezzanine card with the smallest width, the M-Module.
The line drivers related to the function of the IP cores are decoupled from the main module and are implemented on the USM. The USM simply plugs into the corresponding main PMC or main M-Module (Figures 2a and 2b). The mechanical setup of the USM provides maximum space for electronic and mechanical components. This not only includes the available surface of the USM but also the component heights.
Maximum component heights are defined by the different mezzanine standards, and therefore vary. In order to reasonably place a USM within the very small dimensions of a PMC module, a special pass-through connection is used. As for the maximum surface, different mezzanine card formats and the additional space needed for the temperature interfaces on a conduction-cooled PMC module were taken into account.
The electrical connection between the USM and its main M-Module or main PMC consists of two 64-pin plug and receptacle connectors, respectively. J1/P1 makes the connection that transfers the communication signals generated on the USM back to the main module. On this card, J1 is directly connected to the 50-pin front connector.
The signal lines are routed in such a way that there is a sufficient isolation distance to develop a USM with four electrically isolated channels, for instance. The second connector, J2/P2, is the electrical connection between the main module’s FPGA and the USM. Among others, 12 ground pins are evenly distributed over the complete connector. The USM is supplied with 3.3V and 5V using two pins each.
Since I/O functions are realized in the FPGA, the lifetime of a PMC module or M Module no longer depends on the availability of commercially available components. Even after 10 years and more, older IP cores can be updated and brought into a newer and maybe larger FPGA. Both M-Module and PMC main modules and the USM plug-in modules are designed for an operating temperature of -40° to +85°C. To meet demands for increased shock and vibration resistance, the boards are equipped with soldered components and sturdy connectors.
The first USM-based standard PMCs brought to market include a four-channel CAN bus interface, a four-channel RS-422/485 interface, dual Fast Ethernet and a reflective memory PMC module. To implement these functions, four different USM plug-in modules could also be used to bring the same functionality to M-Module mezzanines.
Broad Range of Applications
Due to the universality of the USM concept, there are no restrictions regarding the target markets and the type of application. A number of implementations are possible from machine control in industrial settings to test and simulation systems in automobiles or in telecommunication up to monitoring and control in mobile and safety-critical applications. However, the following are a few real-world examples of how the USM concept is being implemented across various applications (Figure 3).
Figure 3: Cost-saving USM-based modules are employed in a number of applications from light duty industrial to heavy, mission-critical.
In one of the first applications to use M-Modules as a hardware platform, the USM-based M-Module was an addition to existing CompactPCI systems and also to industrial PCs where a number of other M-Modules were already being used. Since the desired functionality was very specialized but had to be combined with different functions on a single module, USM provided the fastest and least expensive solution.
The FPGA contains a CAN bus controller already available as a standard core as well as a K-/L-Line interface. Apart from the CAN bus and K-/L-Line line drivers, the USM includes a FlexRay controller and digital I/O in hardware. The USM-based M-Module is a part of computers used to test anti-lock braking system (ABS) control devices inside vehicles and is used both in the lab and in series production as well as for reprogramming during maintenance.
In an application for testing systems for the aircraft industry, PMC main modules are the platform of choice. Here, PowerPC-based VMEbus computers are used in simulation, validation, test and maintenance. Interfaces such as ARINC429/629, MIL-STD-1553 and AFDX, which may vary from one application to another, are integrated using PMC modules. In order to guarantee that current projects are future-safe, controller components for airplane fieldbuses, such as ARINC429, are implemented only as IP cores in the FPGA, with the line drivers realized on a USM plug-in module. The performance of the FPGAs is sufficient for up to 32 channels in the system with a data rate of 100 Kbits/s each.
Comprehensive Development Package
A considerable range of functions implemented as IP cores are now available on the market, for example from opencores.org. For its own boards, MEN Micro uses a continuously growing number of IP cores designed on its own on the basis of Wishbone, which are also used to complete customized solutions. With the growing acceptance of FPGA-based approaches, more users can develop and integrate their own cores.
To do this—as is the case with the USM concept—users should get support from the hardware manufacturer. For this reason, there is a comprehensive development package for M-Modules and PMC modules based on USM that enables the user to easily and quickly turn very specific I/O requirements or individual functional combinations not available as a standard configuration into series products.
The USM development package includes a main M Module (M199 equipped with an FPGA, 32 Mbyte DRAM and 8 Mbyte flash) or a main PMC module (P599 equipped with an FPGA, 32 Mbyte DRAM and 2 Mbyte flash). In addition, the package includes a bare USM plug-in module, a test board where I/O signals from the FPGA are led, a SCSI cable for connection between the main module and test board as well as an FPGA package. A debug interface for the Nios soft core is included on the main modules.
The FPGA package comprises the Nios processor, memory control, connection to the PMC or M-Module and the Avalon/Wishbone bridges. For development of IP cores on the standard Wishbone bus, the Wishbone BusMaker tool from MEN Micro is included. In order to use the Nios core and to develop IP cores on the Avalon bus, users also need Altera’s Quartus II design environment including the SOPC builder.
USM as an Open Specification
To give access to the new concept to other vendors of PMCs and M-Modules, MEN Micro has published the entire USM specification. It documents the mechanical and electrical characteristics as well as environmental requirements for the different main modules and the corresponding USM plug-on cards.
The driving requirements for the development of this concept included a simple design structure, low production and design costs, ruggedness for harsh and/or mobile industrial environments and a maximum size of the USM module. The same USM was designed to be as large as possible and still be pluggable onto M-Modules, PMC modules or XMCs and conduction-cooled PMC modules. It is even possible to use two USM cards on one Eurocard. For the user, new designs of future USM-based PMCs and M-Modules primarily involve the FPGA content, and therefore save significant development time and costs.
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