Data Acquisition with Small Modules

High-Speed Digitizers Recapture Innovation as ADCs Yield to FPGAs

Incremental advances in electronic components no longer limit the potential for wideband data acquisition systems.


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Prior to the new millennium, skilled hardware engineers pushed the technology envelope with inventive wideband digitizer designs leveraging an assortment of discrete logic integrated circuits (ICs): counters, registers and simple programmable logic devices. This environment led to unique products driven by hardware engineers where one manufacturer’s digitizer could have significant fundamental differences in design layout and capability versus other digitizer products. However, around the turn of the century, high-speed digitizers became increasingly difficult to develop due to the compounding effect of IC tolerance errors, which resulted in design timing issues.

Fortunately, as ICs began to fail to meet the needs of rising analog-to-digital converter (ADC) sampling rates, early field programmable gate array (FPGA) devices were just beginning to enter the market. Though these early FPGA devices were not the data processing juggernauts they are today, they did allow for digitizer designs to consolidate what once spanned about 50 to 100 ICs to a single FPGA package. The result was much tighter timing and truly synchronous designs that no longer suffered compounding time deviations from IC to IC.

Utilizing FPGA components clearly solved an important industry problem that was in dire need of a solution, but it also created an interesting side effect. Digitizer products began to homogenize across all designers and manufacturers, where new digitizers seemed to be little more than the latest ADC connected to the latest FPGA, which begged the question, “Where is the innovation or invention?”

The last couple FPGA component generations have elevated their processing capabilities to the extent that not only can they handle the raw data rates of the leading ADCs for various onboard data routing and handling requirements, but they also are providing ever increasing processing resources (above and beyond ADC data loads) for real-time data processing applications. Given the meteoric rise of FPGA processing resources in a relatively short period of time, the future answer to the question concerning the whereabouts of digitizer innovation or invention will likely come from the creative hands of FPGA logic designers.

Table 1 shows the trend for 14-bit ADC sampling rate increases over the past decade. The devices selected were among the leading sampling rates for 14-bit ADCs at the time of their release. Notice that ADC sample data rate loads increased by about a factor of 4:1 over the course of seven to eight years.  

Table 1
ADC sampling performance factor increases since 2002

Compare the ADC performance growth rate over this same period with the FPGA processing performance growth rate in Table 2, and it becomes quite evident that there is a large disparity in the rate of FPGA processing resource growth versus the leading high dynamic range ADC data loads. Figure 1 is a graph that plots the performance factor values from the two tables relative to each other.

Figure 1
14-bit ADC Data Load Increases Versus FPGA Processing Performance Increases since 2002

Table 2
FPGA processing performance factor increases since 2002

FPGA Performance

Xilinx FPGAs were selected for the relative ADC performance comparison to minimize difficulties in comparisons across manufacturer components and also because Xilinx is the FPGA sales leader. The components selected were an attempt to find components of similar class across the Virtex II to Virtex-6 generations of FPGA components. The component selection process for finding these similar components across generations is not so black and white, which admittedly leaves room for some error, but the overall general trend is undeniable.

Since 2004 and the release of the Virtex-4 FPGA, the primary processing elements within Xilinx FPGAs are the logic cells and the DSP48 slices (PowerPC processors are also available in some models, but are not a focus in this article). While difficult to directly quantify performance capabilities of one versus the other (since they tend to specialize in different operations), industry experience and component history indicate that the logic cells and DSP48 slices deliver comparable processing magnitudes when considering all logic cells versus all DSP48 slices for a particular FGPA package. Again, similar to the FPGA component comparison selection process, equating the relative capabilities of all the DSP48 slices in a package relative to all the logic cells is not so black and white, but it is clear that both resources can deliver significant processing capabilities to real-time applications, and neither resource has significant capabilities over the other.

The graphs in Figure 2 show the FPGA performance factor increases—derived from data in Table 2—and the relationship between different FPGA component generations of Xilinx FPGA devices.

Figure 2
With each next-generation FPGA, processing performance triples about every two years.

Table 2
FPGA processing performance factor increases since 2002

This progression comparison provides a sense of relative capability between the FPGA devices as well as data for how the “Estimated FPGA Performance Factor” numbers were established. Based upon these numbers, both resources appear to approximately triple for each new component generation. It should also be noted that the clock rates increase by about 10-20% for each generation, resulting in an effective performance growth rate slightly greater than the resource counts alone would indicate.

However, is such an exponential performance factor path sustainable? To answer this question, initial analysis of the increased next-generation FPGA resources relative to the Virtex-2 shows a general x3 increase across all FPGA resources (Figure 3). So far, the exponential theory holds. However, analysis of the performance factor increase of all FPGA resources relative to the predecessor FPGA model reveals a different story.

Figure 3
Relative increment of different FPGA resources for different FPGA generations using Virtex- II as a basis.

Figure 4 shows an interesting trend regarding the exponential growth factor of the DSP slices. From the Virtex-4 to the Virtex-5 to the Virtex-6, the exponential performance factor slows linearly, from x4 to x3 to x2, as new FPGA generations are released. In contrast, the logic cells growth shows little variation, hovering between 2.7 and 3.3 for each FPGA generation.

Figure 4
Relative increment of different FPGA resources for different FPGA generations using the previous generation as basis.

The DSP slice performance factor decrease isn’t unexpected. Great advances are often followed by a gradual normalization process. Yet, despite the slowdown witnessed with the DSP slice, the x3 logic cell growth trend continues for a few FPGA generations, where an incredible amount of logic resources will be available even if the DSP slice growth were to slow down and stay under x1.5 per generation.

To highlight the exponential processing capacity in a practical sense, consider that in 2004, digitizer cards could acquire 160 MSPS of 16-bit data for a single analog channel and select up to 10 DDC channels containing 3 MHz of narrowband data with a logic package running on an embedded Xilinx Virtex-4 FX60. This process consumed nearly all DSP resources within the Virtex-4 FX60 FPGA.

Just two years later, when Xilinx released the Virtex-5 SX95 in 2006, digitizer cards could acquire two analog channels at a full rate of 400 MHz at 14 bits, where the FPGA not only handled the same DDC capability, but also allowed the addition of real-time FFT processing and data averaging modules.

Current Capabilities of Embedded Logic 

In 2009, Signatec, Inc., a manufacturer of high-speed data acquisition, real-time processing and arbitrary waveform generation systems for advanced radar, signals intelligence (SIGINT), ultrasound, medical imaging and other high-speed communications applications, released a PCI Express-based, high-speed digitizer leveraging the Virtex-5 SX50 and SX95 FPGAs with embedded fixed signal processing packages (Figure 5).

Figure 5
PX14400-SP95 and Signatec’s V5 SX95T-Based Processing Elements (at 400 MSPS, 2 Chs, 14 bits)

The left side of Figure 5 exemplifies a common wideband capture scenario, where the PX14400 digitizes 14-bit data at 400 MHz for a total capture band from near DC to 200 MHz.  Inside this greater 200 MHz bandwidth is an intermediate and smaller band of interest positioned at the center frequency (Fc). The ADC digitizes the input signal and passes data to the “Standard Signatec Logic” (SSL) module, which contains all PX14400 general-purpose product services.

Figure 5
PX14400-SP95 and Signatec’s V5 SX95T-Based Processing Elements (at 400 MSPS, 2 Chs, 14 bits)

The SSL, contained entirely within the first V5 LX50T FPGA, connects directly to the ADCs, PCIe host bus and to a second V5 SX95 FPGA. This second FPGA is dedicated to real-time data processing and incorporates all remaining diagram elements.

In this fixed capability logic kit (FLK), the first element in the processing chain is the numerically controlled oscillator (NCO), which allows for modulating the signal band of interest to another center frequency, usually baseband. FIR filter stages follow the NCO and allow data decimation in steps of x2 from 23 up to 212. The output of the filters can be either real or I&Q format.

Figure 6 shows the characteristics of the x2 decimation filters, where the stop band is sufficiently attenuated by 90 dB or better, which exceeds the dynamic range for a 14-bit signal digitizer. Data decimation occurs in x2 increments repeatedly until achieving the desired decimation rate.

Figure 6
Frequency response of the x2 decimation filters

Windowing and FFT processing stages immediately follow the filters. The FFT window is fully programmable with variable FFT sizes from 64 to 4096 points supported. The output from the FFT is either magnitude squared or complex, which then passes into a programmable data averager with up to 216 accumulations possible to complete the processing elements. Any processing element in the FLK can process data in-line, as shown in the diagram, or be bypassed.  

Next-Generation ADCs

The previous section detailed the type of real-time processing capabilities that are currently in the digitizer market and running on the Virtex-5 SX50T/SX95T devices. Using the recently released state-of-the art 1 GHz, 12-bit ADC as an example, today’s 28nm Virtex-6 FPGA family equivalent of the Virtex-5 SX95T will possess the capabilities to handle the x2.5 jump from the previous 400 MHz, 14-bit ADC digitizer processing example (and likely with some additional resources to spare). This result indicates that not only can the next-generation FPGA components more than handle the state of the art for 14-bit ADCs (as established), but they can also effectively handle the increased data sampling rate demands of the highest sample performance 12-bit ADCs when implementing the same DDC, FIR filter, FFT and data averaging example program for the 400 MHz digitizer.

When compared to the advances in FPGA processing capabilities of the same time period, ADC sampling rates are increasing at a slower rate than FPGA processing resources. Given that FPGAs triple processing elements about every two years and ADCs double sampling rates every 2.5 to 3 years, by 2016, FPGA processing capabilities will outpace the ADC data supply load by about 6:1. Should this trend continue, in 10-12 years, the ratio could be over 30:1.

Such large ratios of increased embedded processing performance above and beyond the real-time processing capabilities possible today positions the high-speed data acquisition and signal recording industry upon the precipice of a design revolution, where a wave of innovation and invention will birth creative new paradigms. The driver of digitizer technology, which to date has mostly been ADC driven, will likely transition to an FPGA-centric model where product capabilities will be increasingly defined by the embedded processing. 

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