P/C-ASPs: A New Class of Devices
The Application Services Platform: A New Class of Device for Embedded Development and Systems
A new class of device is appearing in the world—the Application Services Platform or ASP. With the integration of CPU, standard yet configurable peripherals and a programmable fabric, all the services needed to develop an application are available to the developer on a single chip.
BY TOM WILLIAMS, EDITOR-IN-CHIEF
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There have been many attempts over the years to achieve a highly integrated system-level device on a single piece of silicon. There have been ASICs, ASSPs, SoCs and more. There have been efforts to implement entire systems as soft IP on FPGAs. All of these have run up against issues like the need for high volume to justify costs or the need for developers to become versed in esoteric languages such as Verilog or HDL. Often special needs, like a certain amount of signal processing, have required the addition of a DSP as coprocessor with attendant costs, latencies and the use of specialized coding knowledge.
While these issues have certainly not disappeared, we are now going in a positive direction with a class of devices that integrate a 32-bit CPU, a selection of commonly used peripheral interfaces such as UART, USB, GPIO, analog, SATA, I2C, memory interfaces and so on. In addition, they also incorporate a programmable logic fabric based on FPGA technology that can integrate off-the-shelf IP in the form of predefined devices or algorithms and can still be custom programmed for very specialized needs.
All of these common and specialized interfaces can then be made available as digital services to the programmer on the single, integrated device, the Programmable/Configurable - Application Services Platform, or simply the Application Services Platform (ASP). At least three companies are currently implementing ASPs in different forms: Cypress Semiconductor with its PSoC family, Actel with its SmartFusion devices and Xilinx with its “extensible processing platform” architecture. All three families are based on the ARM RISC architecture—the ARM Cortex-M3 for Cypress and Actel, and a dual-core ARM Cortex-A9 in the case of Xilinx. They also differ in the mix of peripherals and the emphasis on analog processing, but all three indicate a new direction for embedded development.
It seems that the trend began in the 8-bit world with the Programmable System-on-Chip (PSoC)3 from Cypress. The PSoC3 is based on an 8051 core and is the answer to the drudgery of sorting through catalogs of hundreds of 8051 variants looking for the right mix of peripherals. Why not just include the most commonly used with configurable digital and analog I/O blocks on a single die and let the user configure the desired mix of peripherals using an intuitive graphical tool? Then stand back and let the software guys program it in C as they are very capable of doing.
More recently, Cypress introduced the PSoC5 (Figure 1), which uses the same set of peripherals but brings in the 32-bit ARM Cortex M-3, which can run both ARM’s Thumb 2 16-bit code or 32-bit code. PSoC5 consists of three components: the processor layer includes the CPU core, memory interfaces, EPROM, DMA controller and interfaces for CAN 2.0, I2C and USB 2.0.
The three layers of the PSoC architecture are, except for the processor core, the same for both the PSoC3 and PSoC5 devices. I/O can be routed to selected external pins on the chip and to internal elements via the programmable routing and interconnect block.
The I/O portion is highly configurable by means of the graphical tool called PSoC Creator. One part is the digital subsystem, which consists mainly of an array of universal digital blocks of programmable logic that can be defined as UARTs, timers, multiplexers, LCD drivers and more by use of PSoC Creator. The analog subsystem similarly is built up with elements that can be programmed as DACs, ADCs, op-amps, comparators, etc. that can be set up from a library of pre-built components, which can be configured further using the tool. In addition, there is a two-channel digital filter block. Analog channels can have up to 20 bits of resolution.
One other element provides a highly configurable interconnect between the elements on the processor layer, the configurable block of the digital and analog subsystems, and the external pins on the chip via GPIO ports—all of which can be defined with PSoC Creator. The tool also lets you assign names to the elements that then form part of the API that is available to the programmer. The programmer simply needs to know the names and functions of the API and can proceed to start developing code.
And Now We Add the Fabrics
Taking the PSoC idea to its logical conclusions—with enormous consequences for embedded system developers—are two FPGA companies, Actel and Xilinx. Each has independently come upon the idea of taking the processor with its array of configurable peripherals and adding the programmable fabric of a field programmable gate array. This is a fundamentally different approach from the earlier method of embedding soft CPUs, or in some cases hard-wired processors, in the programmable fabric. In these designs, the programmable fabric plays the role of a programmable/configurable peripheral field.
In both the SmartFusion product family from Actel and the new architecture announced by Xilinx, the fabric is configurable in the sense that the system architect can specify and bring in predefined peripheral devices as well as pre-written algorithms for custom coprocessing. It is also programmable in the sense that specialized soft devices as well as algorithms can be programmed from scratch if need be.
SmartFusion uses a microcontroller subsystem based on the 32-bit ARM Cortex-M3 with a 10/100 Ethernet MAC, two each of SPI, I2C, UART and 32-bit timers. In addition there are 512 Kbyte of flash and 64 Kbyte of SRAM on-chip along with an external memory controller and a DMA controller and up to 41 MSS I/Os (Figure 2).
The SmartFusion devices from Actel are based on the ARM Cortes-M3 and include in addition to the programmable fabric, a programmable analog subsystem with an analog compute engine (ACE).
The Xilinx “extensible processing platform” architecture has gone full bore to a dual-core microprocessor and is based on the dual-core superscalar ARM Cortex-A9 with the NEON 128-bit SIMD engines. The microprocessor subsystem includes a large number of pre-built peripherals including GPIO, tri-mode Ethernet (10/100 Mbit and 1 Gbit), USB 2.0, UART, CAN, I2C, SDIO and SPI. In addition, there is a variety of external memory interfaces including flash and NAND controllers, parallel and DDR controllers. Pre-implemented on the FPGA fabric are additional configuration and security interfaces, including a system monitor, 12-bit ADC and Gen 1 and 2 PCIe (Figure 3).
The extensible processing platform architecture announced by Xilinx places emphasis on a high-powered dual-core ARM Cortex-A9 with a wide variety of pre-defined peripherals in addition to the programmable fabric.
Both device families have on-chip analog interfaces, although the SmartFusion devices appear to have placed greater emphasis on the analog aspect, making it a complete analog subsystem. An analog compute engine (ACE) offloads the CPU from analog tasks—it incorporates a sample sequencing engine and a post processing engine. The analog section also incorporates 12-bit DACs at up to 600K samples per second and up to ten 50ns comparators. In all, there are up to 32 analog inputs and 3 outputs depending on which version of the device is chosen.
In the SmartFusion family there are currently three members with 60K, 200K and 500K gates respectively. Device configuration is stored in on-chip flash memory that can be locked against tampering and reprogramming. The SmartFusion devices have up to 128 FPGA I/Os depending on which device is chosen. Xilinx has not yet released product-specific data as to the sizes of its arrays or the number of I/Os.
Programming of these ASP devices at the microcontroller/microprocessor end is straightforward with the wide variety of ARM development tools that are available. Configuration and programming on the fabric end are supported by company-specific tools. Of course, each company will supply and support a selection of ARM tools, but the developer is free to use whichever ones appear most suitable and familiar. There will, of course, be a number of tools available to shield the developer from having to deal directly with FPGA-specific programming languages such as Verilog and Hardware Description Language (HDL), which are still the realm of specialists.
There are graphical UI tools for the use of pre-existing IP libraries for both environments as well as company-specific FPGA development tools for programming, timing analysis, power optimization, etc. The interesting question is how this new class of devices will affect the development culture. We are predicting that it will catch on and grow due to a number of very specific advantages. The first is inherent in the name “application services platform.” The idea is to present to the application programmer on a single chip all the services that will be needed by the application in a form that the C programmer can readily understand and incorporate into the application code.
An ASP literally contains all the devices, common or custom, short of main memory, mass storage and display, that an embedded device may need. These are put together during the configuration stage when peripherals are selected and configured, or in the case of the programmable fabric, downloaded, connected and/or created from scratch. Obviously, this latter part may require differing levels of specialized expertise, such as that of a DSP specialist who can create needed algorithms in the fabric. Such components would be specified by the system architect. Once they are created and incorporated however, they can be utilized by the application programmer using his or her established skills.
The savings in parts and in the bill of materials have the potential to be impressive. For example, suppose a medical device requires a couple of DSP algorithms to process an ultrasound signal. Normally, this might require a DSP coprocessor and attendant software and programming, which would run up the parts costs, development time and inventory. Having a specialist create the small set of needed algorithms that could then be loaded into the FPGA fabric could represent significant savings on all these fronts and also improve performance. The result would be a number of algorithms that could process inputs without intervention of the processor, making the digital results available to the application code. An arbitrary number of such algorithms could run in parallel on the fabric significantly reducing latencies. All this still happens on the same chip, obviating the need for a coprocessor, extra board space and power consumption.
Another potentially large advantage of ASPs is their effect on bills of materials for what could be a family of devices. Simply changing the programming and configuration of the same physical device could yield radically different systems and subsystems for applications such as medical devices, transportation systems, system management applications and many, many more.
What we are seeing with the advent of the Application Services Platform is the emergence of a new class of devices that will have a very big impact on the design of, especially, small, handheld, mobile and low-power systems. These first three incarnations will certainly not be the last, from these companies and from others. We already notice a difference of emphasis between the Actel SmartFusion family and the extensible processing platform architecture being announced by Xilinx. SmartFusion places more emphasis on a programmable analog subsystem while Xilinx appears to be heading for a family based on a high-performance dual-core CPU. It is not inconceivable that there may be additional processor architectures that will find their way into an ASP architecture, perhaps with emphasis on graphics and user interface. There will no doubt be partnerships that will be formed between processor manufacturers and programmable logic vendors. By the way, there is a limited number of the latter, so dance cards may begin filling quickly.
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