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FPGAs – The Logical Choice

COLIN MCCRACKEN & PAUL ROSENFELD

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The ability to customize logic has underpinned the electronics industry since the early days of the 74xx glue logic family. Whether for simple chip selects, shift registers, registers, or flip flops, these building blocks proved invaluable to designers in all parts of the market. A far cry from the automated environments of today, these popcorn 7400-series parts were arranged like Legos to implement 8-bit processing cores, buses, communications and I/O.

Moore’s law advanced the design task from Karnaugh Maps to EDA tools, and the domain gradually shifted from board-level to chip-level design. The doubling of transistors every 18 months took us from small-scale integration (SSI) to medium- to large- to very large-scale integration (VLSI), and flexible gate array structures. One-time-programmable ICs and test vectors gave way to complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs) that load their “brains” from serial flash firmware upon power-up, immersing us in a veritable alphabet soup of four letter acronyms. With easy field upgradability, advanced design tools and high-level “languages” like Verilog and VHDL, hardware design has evolved to resemble software coding.

Programmable logic appeals equally to the few designing smart phones as well as the many designing wide ranges of small(er) volume non-consumer devices. How do these technological advances impact our small form factor corner of the world? Regardless of which 4-bit microcontroller or 64-bit RISC or x86 microprocessor architecture, CPLDs play a critical role in interfacing system buses to I/O—or, if you prefer the outside-looking-in perspective—how the real world can access processors. Easy-to-interface parallel buses required address decoding, FIFO buffers, interrupt- and DMA-generating logic, not to mention computational or control logic behind the analog front-ends.

The next step up in terms of complexity is FPGAs with integrated RISC processor cores. Some of the FPGA vendors push their own integrated processor cores, with compilers and kernels, while others embed standard PowerPC or ARM cores in their chip offerings. Cores can also be in “soft” form (synthesizable Verilog or VHDL), which are merged and simulated with custom logic before being synthesized into gates. Configuration options can be selected prior to synthesis, giving a measure of flexibility. “Hard” cores are optimized at the transistor level, saving cost and die space while increasing speed and the gate count available for custom logic.

FPGA suppliers have created the impression that such smart devices will replace discreet microprocessors. Have no fear. This is nothing more than overzealous marketing hype. Even so, these chips remain quite useful for distributed control systems and smart I/O (dare we say “intelligent I/O?”).

As parallel buses give way to high-speed serial bus topologies, design challenges are increasing while fewer devices are available that meet interface requirements. The acronym “SERDES” refers to the serialize / de-serialize nature of the point-to-point interconnect. This is a far cry from traditional multi-drop local buses. A SERDES PHY (physical layer) must be implemented to interface to the 1.25 GHz (2.5 Gbit/s) PCI Express link. This ain’t your mother’s FPGA.

Some devices have not only the requisite PHY but also a bus bridge or a registered parallel bus interface behind it in “hardened” form. Otherwise designers need to integrate a Verilog or VHDL “socket” type of interface with their custom logic, and away they go.

One downside for FPGAs is their use in stacking architectures, especially in sealed enclosures. The incremental power consumption over previous parallel buses is stark, reaching 0.5-1W or more. Although not a big deal for line-powered systems, every milliwatt counts for battery-powered devices, from handheld instruments to forklift HMIs to vehicle computers. Besides battery life, heat removal is a necessary design consideration.

FPGAs can be “multi-bus” by connecting to both high-speed and low-speed buses, with internal circuits attached according to the data bandwidth needs. This approach is quite optimal, as interfacing low-speed I/O to PCIe is akin to sipping from a fire hose. Examples of low-speed buses include LPC (low pin count) Bus, SMBus (system management bus for x86) / I2C, and—yes, finally gaining popularity in the x86 space—the SPI bus (serial peripheral interface). Each of these takes very few pins, simplifying FPGA design tasks.

Conserving board space is generally more important than minimizing cost in the smallest form factors. Rather than having myriad distributed timing circuits (analog or digital), separate bus and I/O transceivers, smart I/O controller chips, power sequencing logic, GPIOs or discreet CPLD for each section of a design, FPGAs are the logical choice to combine all these functions into a single component for I/O-oriented small form factor designs.