FPGA Family Spans the Spectrum
28 nm FPGA Device Portfolio Addresses Continuum of Design Requirements
A set of three product families based on a new 28 nm technology offers a range of configurable and hard-wired options on devices addressing applications from handheld/mobile to high-end communications in an effort to optimize power, cost and performance.
TOM WILLIAMS, EDITOR-IN-CHIEF
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In these pages we have written quite a bit lately about the quest for the perfect ASIC. It is some mystical combination of programmability, hardware configurability, performance, cost, low power consumption and the availability of good development tools. In a sense, the first microprocessor was the beginning of this quest—an integrated circuit that could be adapted to different applications by virtue of writing the appropriate code. So much has come to the party since then in terms of integrated peripherals, hardware-defined functions, programmable logic and all the rest. Yet the quest continues.
This time it comes in the form of a rollout of three major product families from Altera that incorporate select process technology combinations in 28 nm, a 28 Gbit/s transceiver technology, new product architectures and system IP. In addition, Altera has taken its established Hardcopy technology—the ability to convert FPGA-based designs seamlessly into hard logic to create custom ASICs—and made it into what it calls an Embedded Hardcopy Block (EHB). An EHB can coexist with an FPGA fabric on the same silicon die (Figure 1).
Embedded Hardcopy Blocks (EHBs) are areas within the FPGA fabric that can be populated with hard gates for IP that has been proven and selected for hard implementation to save power and cost, increase performance and free up logic elements.
Another technology wrinkle is what Altera calls partial reconfiguration, or—without turning off the power to the chip—the ability to isolate a portion of a device to take it offline and reprogram it. For example in a communications device, one could add another client without taking down other ports on the device or interfering with ongoing network traffic.
The product/technology rollout consists of three families: the CycloneV equipped with 5 Gbit/s transceivers and running at under 5W; the ArriaV with 10 Gbit/s transceivers and coming in at under 10W power consumption; and the StratixV, which boasts the 28 Gbit/s transceivers, a clock speed of greater than 350 MHz, and what Altera considers the “lowest power in its class.” In addition, Altera is also formally announcing its 28 nm HardcopyV ASIC family onto which proven FPGA designs can be fully migrated for the associated performance gains and cost/power savings.
In an effort to serve a broad range of applications that require different trade-offs of performance and power consumption, Altera utilizes the 28 nm technologies of Taiwan-based TSMC. For the 5 Gbit/s and 10 Gbit/s families, it chose the 28LP technology that optimizes for optimal power and cost, while for the 28 Gbit/s StratixV high-performance line, it chose the 28HP process technology that aims for an optimal combination of power consumption and performance speed.
The 28 Gbit/s transceiver technology featured in the StratixV parts is based on a proven core transceiver design, which is also the basis of the 5 Gbit/s and 10 Gbit/s transceivers. It is optimized for optical chip-to chip communication such that a 100 Gbit Ethernet channel can be accommodated by four 28 Gbit/s transceivers for short trace connections to onboard optical modules. The rest of the bandwidth is used for error correction. In addition, ten 10 Gbit I/O channels can be plugged into Ethernet ports for outside communication. Backplane communications up to five feet are possible at 14.1 Gbit/s. This greatly reduces the number of traces needed for high-speed system-internal data transfers.
Tailored Memory Architectures
In order to more specifically target the classes of applications served by the three FPGA families, Altera has implemented three different flavors of on-chip memory. The CycloneV family is aimed at mobile devices like handheld projectors or video surveillance cameras that require a relatively large number of memory ports for many small buffers to handle data from things like finite impulse response (FIR) filters and things that entail wireless signals and converting them and then outputting the results. For this the CycloneV has a M10K memory to enable high buffer performance.
For the mid-range ArriaV, the memory has more bits per silicone area for line cards in systems such as remote radio units or broadcast equipment or network line cards. Here a relatively large number of bits per silicon area are needed in relation to ports to store and efficiently move data packets. These mid-range devices use an M20K memory block to address their needs. Another memory block that will combine with both the M10K and M20K blocks is called the memory logic array block (MLAB), which is present in all the devices. The MLAB is a small 640-bit chunk of RAM that is sprinkled throughout the architecture to make possible small FIFOs and delay elements where needed.
In terms of the external interfaces to memory, the two lower-end families have been designed with hardened interfaces to accommodate the most popular methods of accessing external memory. That is not to say that one cannot design a custom memory interface using the programmable logic, but for the sake of convenience there are pins on the chip that are hardware memory interfaces: 400 MHz DDR3 for CycloneV and 533 MHz DDR3 for ArriaV.
On the high end, however, customers still want to roll their own although IP exists to support 800 MHz DDR3 DIMM. But, of course, there are tweaks and special tricks that vendors make at this level and want the flexibility. For instance, there is also a push to use reduced latency DRAM (RLDRAMIII) and quad data rate (QDRIII) memory to name a couple. So Altera has not created a hardened memory controller interface for the StatixV family. This means more work but the ability to put in the “special sauce” at this level.
In terms of other I/O, the low-voltage (3.3V) CycloneV is tailored to support industrial Ethernet variants like EtherCAT for applications in industrial automation, while the ArriaV and StratixV have 1.25 Gbits and 1.4 Gbit/s LVDS interfaces respectively. Altera has taken the initiative to harden some of the I/O technology in the different device families that seems to be popular, stable and appropriate to that class of device. In fact, there could be potential changes or additions to the on-chip hardened IP depending on customer demands.
For Altera, this would be a straightforward matter given that they have included the EHB technology as an option in all three families. Deciding exactly what to harden and what to leave open to customer configuration can be tricky, but there are also several “no brainers.” For example in the CycloneV family, in addition to the hardened memory controller mentioned above, there is an interface for PCI Express Gen2 x1. In the ArriaV that is expanded to PCIe Gen2 x4 and triple speed (1/10/100) Ethernet (TSE). After all, nearly everybody can find a use for that! ArriaV also offers a boon to DSP designers in the form of variable precision DSP. That means that beyond the typical (and popular) 18 x 18 element multiplier, one can choose different levels of precision such as 9 x 9, 27 x 27 or even 54 x 54. All these elements can be incorporated into the device architecture in addition to the core FPGA fabric to enhance the options for the developer (Figure 2).
The example of the StratixV architecture shows that in addition to the core FPGA logic, there are variable precision DSP blocks, M20K memory blocks and embedded hardcopy blocks. In addition, the transceiver structure can support 10G ports that can aggregate to 100G external Ethernet along with 28 Gbit/s transceivers that minimize the number of traces for chip-to-chip communication (28 Gbit/s) and backplane communication (14.1 Gbit/s).
In the StratixV family, the PCIe hard offering goes up to PCIe Gen3 x8 along with 100 Gbit/s Ethernet. In addition, there is a hardened IP block for the Interlaken high-speed chip-to-chip protocol, which is quite logic-intensive, and having it in hardened logic not only offers cost and performance benefits but also takes up far less die area leaving room for more programmable logic elements.
Finally, the advent of the Hardcopy technology in both full custom ASIC form and in EHB form gives designers a host of options. One can order parts with certain other, often proprietary IP in EHBs once the volume and acceptance of a product makes it economical, yet one can with this option also retain the option to implement certain and even newer ideas in the programmable fabric of the device. Or, once volume and business model dictate, one can order a full custom ASIC that takes a proven FPGA design and delivers it in the form of a whole 28 nm, 500 MHz IC with 14.1 Gbit/s transceivers.
The partial reconfiguration option also allows those who have programmed their original designs to allow for it, to add or change programmed IP with the chip in circuit and with other elements on it running. The emphasis here is that the design must be able to accommodate the reconfiguration option in advance by reserving programmable fabric in a useable manner.
So the lesson here is that there may not be one single device that is the ultimate ASIC, but there could well be a family of devices that shares technology, architectures and features in a continuum that lets designers pick the appropriate variant to meet their needs and to move easily up and down the line of capabilities using a uniform set of design tools—in this case the Quartus II suite and others to come—to get closer to that elusive grail.
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