The Dance of Optimization: Waltzing Down to the Silicon
TOM WILLIAMS, EDITOR-IN-CHIEF
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There appears to be a transition taking place that will significantly influence the way embedded systems are designed. For some time we have been witnessing developments in small form factor modules in various creative incarnations. The venerable PC/104 form factor continues its healthy acceptance along with such derivations as PC/104 Express and SUMIT-ISM, other stackable form factors like EPIC and EBX, and COM Express and its variants now shrinking down to the sub-credit-card “ultra” size. The list goes on.
These innovations are the result of the push to find optimal solutions to a variety of problems and applications. That is what engineers do for a living. One such class of problems that cuts across the efforts of stackable and COM approaches has been how to combine the general-purpose functionality (CPU, memory) with the more specialized functionality (I/O). That gets far less than straightforward when you try to optimize the combination for size, cost, performance, power consumption and ruggedness. Still, the efforts and the results at the small module level have been mighty. It now appears that this titanic struggle will increasingly be taking place at the silicon level.
Advances in programmable logic and the ability to combine it with hard-transistor IC implementations on a single die are leading to rapid advances. In this issue of RTC we have news of a major rollout from Altera and the productization of efforts by Xilinx that were first announced last year. In addition, Microsemi and Cypress Semiconductor already have products on the market with more to come. It has long been assumed that from a performance/size/power perspective, hard-wired ASIC would be the ideal solution. Little considerations like cost, however, have kept that from happening.
Now, however, the effort to combine general programmability with application-specific circuits and functionality is moving from board to die. Lest I be misunderstood, this is not going to spell the end for small modules, but it may make them smaller and less critical in terms of form factor. Still you have to get the results of all this processing off the board and into the system and the real world, which is not measured in nanometers. Boards and connector technology have a bright future in the world of these developments.
Many of these efforts combine a CPU with a programmable logic fabric as is the case with the Microsemi SmartFusion, the Xilinx Zynq, the Cypress PSoC and the combination of an Intel Atom processor with an Altera FPGA fabric in the Stellarton module. The latter has not (yet) combined these two elements on a single die and nobody is talking, but, well . . . it looks like a natural next step. In addition, Altera has just announced the rollout of its 28nm technology in the form of three families of FPGA devices. While these do not explicitly include an on-chip CPU, the Embedded Hardcopy Block (EHB) technology that allows the implementation of hard transistor circuits in the same die with the FPGA, makes that at least theoretically possible as well. Altera also offers the ability to take a proven FPGA or FPGA/EHB combination and move it directly to a fully hard-transistor ASIC implementation with the attendant advantages in cost, power, performance and size.
And thus the general-purpose programmable functions of the CPU and the application-specific functions of the I/O subsystem—which have heretofore been accomplished with stackable or COM modules—become available on a single chip and at costs that no longer need be justified by huge volumes. The days when developers sent an ASIC design off to the fab and then sat staring blankly at a revolver on their desks hoping that some flaw would not turn up in the finished part may now mostly be over. You get to fully check out the FPGA-based design in the deployed product, correct any errors and then when more modest volumes and greater confidence allow, move it to the fully hardened part.
Of course, the existence of these parts that have been dubbed by some as Application Services Platforms (ASPs) does not fully bridge the gap between software and hardware design. Writing C code for a well-known processor architecture such as the ARM is still a different discipline from developing hardware functions or implementing hardware algorithms on an FPGA. Advances in development tools have certainly helped and have at least greatly aided communication between the two disciplines, but there is more to do.
One of the hopeful developments is that it will become much easier and less costly to experiment to see if it is better to implement a given function in software or hardware and to produce actual data on the differences. This is what we might call another round in the “dance of optimization.” It never ends. The words to the music go something like, “Wow. That’s really cool. But maybe we can tweak this part a little more.” And the band plays on.