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Flash and More: Nonvolatile Memlry

Advances in Nonvolatile Memory Interfaces Keep Pace with the Data Volume

As the capacity of NAND flash devices increases, so does the amount of data that must be transferred on every read and write. In order to avoid degradation of performance, the speed of the interface must increase accordingly.

TERRY GRUNZKE, MICRON TECHNOLOGY

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With the ever-increasing demand for larger nonvolatile memory capacities, NAND flash technology is widely used in a variety of applications today. It is an aggressively scaled technology, with 20nm-class lithography devices currently in production. As the technology scales, page sizes typically increase, which drives the sizes of the data transfers to become larger. To improve performance and maintain latencies, the interface speeds must increase along with the data transfer size (Figure 1).

Figure 1
Transfer Time: As NAND technology advances, page widths and data transfer sizes become larger. The transfer time across the NAND interface must become faster so the bus transfer is not a performance limiter.

If the page widths or number of planes on the NAND device double, the corresponding interface speed should also double to maintain similar data transfer times per array access. This is especially important in high-performance SSDs, USB 3.0, or other high-performance applications where bandwidth can improve greatly due to the high density and the number of devices per data channel (Figure 2) . 

Figure 2
The ONFI 3.0 NV-DDR2 interface (lower chart) enables 400 Mbyte/s per data channel vs. the previous 200 Mbyte/s interface speed (upper chart) supported by ONFI 2.1 NV-DDR interface. LUNs refers to logical units, or dies, per channel.

Another consideration for increasing the NAND interface bandwidth is the possibility of data channel reduction in SSDs. The same bandwidth from the NAND devices can be supplied to the SSD controller with a faster interface and fewer data channels. This can mean fewer pins on the controller, resulting in smaller form factors and lower costs. In March 2011, the Open NAND Flash Interface (ONFI) Workgroup released the ONFI 3.0 specification. This specification includes the newly defined NV-DDR2 interface that enables up to 400 MT/s NAND interface speeds, doubling the frequency of the previous standard.

To achieve a reliable 400 MT/s interface, improved signaling between the controller and the NAND device is required. Since NAND flash is used in a variety of applications, the system topology is an important consideration in determining the features required to improve the interface signaling. Due to the importance of achieving faster speeds for high-computing applications, the ONFI Workgroup decided that a widely used SSD topology should be used for evaluation in determining the features (Figure 3).

Figure 3
Single-channel SSD topology for signal integrity study: The SSD tree topology used to evaluate 400 MT/s NAND interface speeds includes a host controller connected to two NAND packages with four NAND Flash devices per package, for a total load of eight NAND devices or dies (LUNs) on the channel. SSD form factors determine the distance from host to NAND devices.

The SSD tree topology used to evaluate 400 MT/s NAND interface speeds includes a host controller connected to two NAND packages with four NAND flash devices per package, for a total load of eight NAND devices. SSD form factors determine the distance from host to NAND devices.

Interface Features

To allow the NAND interface to attain 400 MT/s, several features were added to the ONFI 3.0 specification. User commands provide the system designer flexibility through optional enablement of these features (Table 1). This provides adaptability for optimal power and complexity versus performance tradeoffs. The features added to the ONFI 3.0 specification are discussed in more detail in a recent Webinar titled, “ONFI 3.0: Enabling 400 MT/s” (http://onfi.org/presentations/).

Table 1
Interfaces and features supported by ONFI 3.0: The newly developed NV-DDR2 interface is backward compatible with the previous SDR and NV-DDR interfaces.

Differential signaling is a method of transmitting information by means of two complementary signals that are 180° out of phase from the original signals. Previous NAND interfaces used a simpler technique called single-ended signaling. Differential signaling offers twice the noise immunity of single-ended signaling, reduced sensitivity to simultaneous switching output (SSO) noise, and mitigated radiated electromagnetic interference (EMI). For the ONFI 3.0 NV-DDR2 interface, differential signaling can be enabled for the read enable (RE) input and bi-directional strobe (DQS) signals. The flexibility of enabling or not enabling each of the complementary signals saves system pins and associated costs when differential signaling is not required.

An external voltage reference input provides the high-speed differential input buffers with a common voltage reference. It is used by the single-ended, high-speed signals that require fast switching and do not have a complementary signal enabled. The use of the reference voltage also achieves additional system noise immunity. This allows tighter setups and holds during data input to the NAND device, providing more system timing margin.

At higher interface speeds VCCQ = 3.3V can no longer be supported due to slew rate and timing budget requirements. Thus, the NV-DDR2 interface only supports VCCQ = 1.8V with reduced signaling. The popular JEDEC SSTL_18 logic switching range provides the reduced signaling and allows use of existing PHY designs for easier NV-DDR2 enablement.

Improving NAND output drive strength tolerances to improve impedance matching with connected traces is an important consideration for signal integrity at increased transfer rates. To address this, the ONFI 3.0 NV-DDR2 interface requires tighter tolerances across process, voltage and temperature than the previous specification. Selectable drive strength settings of 18 ohms, 25 ohms, 35 ohms and 50 ohms are available on the NAND device.

Warm-up cycles during data input or data output provide a configurable number of dummy cycles with no incremental data transfer. Signal integrity of the system is improved by reducing the effects of inter-symbol interference (ISI).

On-Die Termination Techniques

Termination improves noise margins, reduces signal reflections, affects slew rates, and improves the interface signal integrity overall. Figure 4 illustrates the signal integrity improvements with termination enabled. It can easily be observed that the aperture of the data window and the slew rate improve drastically—making it a picture that is worth a thousand words. When on-die termination (ODT) is enabled, the device or host can dynamically select when to switch on the termination circuitry to avoid unwanted power consumption. The termination circuitry on the die consists of a pull-up resistive element and a pull-down resistive element where RTTPU = RTTPD = 2 x RTT.  RTT is the equivalent termination value selected for the device. For each individual die, the ONFI 3.0 specification can provide RTT values of 30 ohms (optional), 50 ohms, 75 ohms, 100 ohms and 150 ohms.

Figure 4
Benefits of Termination: Interface signal integrity improves greatly when termination is provided on the die. Shown above are data traces and corresponding data eyes without ODT enabled (left) and with ODT enabled (right).

While termination improves the signal integrity of the system, it comes at the possible cost of additional power consumption. For example, if a termination scheme requires RTT = 50 ohm, a single I/O could have 9 mA or more current consumption. For a single data channel on an SSD that may consist of 9 to 11 signals with ODT enabled, this could consume 160 to 180 mW. Because of these costs, it’s important that system designers use the minimum amount of termination to achieve the desired I/O performance. ONFI 3.0 provides flexibility to make intelligent termination tradeoffs dynamically and attain the best desired performance at the minimal amount of power consumption.

 

 

Applications and workload determine if the power required to enable termination should be of concern to the system designer. Achieving performance for consumer applications and client-class SSDs does not typically require high NAND bus utilization, so the overall energy per byte in comparing termination with no termination is small. Higher performance is required for enterprise-class SSDs and, consequently, NAND bus utilization is much greater. For these applications, system designers must consider the tradeoffs of performance versus energy consumption because implementing termination can potentially consume 10% to 20% of the total energy.

To address the issue of possible additional energy consumption, the ONFI 3.0 NV-DDR2 interface introduces the matrix termination method, which provides the system designer with a diverse selection of termination schemes. This enables optimal performance at the lowest system power cost. At initialization, the host controller assigns a unique volume address to each individual target in a system. A target can consist of several individual die or logical units (LUNs) contained in the same package. The host then assigns a termination matrix for each individual LUN in the system. Depending on the values defined in the matrix, the LUN enables termination based on the selected volume’s operation. 

Target termination occurs when a LUN is configured to terminate for the volume to which it belongs. Non-target termination occurs when a LUN is configured to terminate for any other volume. Matrix termination provides the ability for target or non-target termination and allows configuration of possible different RTT values for each LUN. In addition, a LUN can terminate for writes to or reads from the NAND device. This provides many permutations of termination schemes and flexibility to design the optimal power versus performance solution. For examples of enabling an ODT matrix in the ONFI specification, refer to www.onfi.org/specifications.

Implementing ODT on the NAND device requires termination circuitry that can increase NAND die capacitance. Unfortunately, the additional bus loading increases the need for termination. The ONFI 3.0 NV-DDR2 interface specification maintains the same input pin capacitance values as the previous specification while adding the ODT functionality. This is challenging for NAND vendors, but it’s also a requirement to achieve 400 MT/s. To reduce the die capacitance cost of adding ODT, NAND designers can choose to use existing output driver circuitry of pull-up and pull-down transistors to provide the termination. The downside of this technique is that the transistors are in saturation when providing termination at the AC signal switching voltages and consume more power than a more linear resistive terminator.

Reducing Pin Count

Lowering controller pin counts and reducing layout space on the PCB reduces cost and enables smaller form factors. Adding complementary signals for differential signaling to enable 400 MT/s is not desirable for overall pin reduction. To offset the additional pins, the ONFI 3.0 specification added a chip enable (CE_n) pin reduction scheme. Several CE_n pins can be reduced to a single shared CE_n pin. Enabling CE_n reduction requires the volume address appointment at initialization, which was discussed earlier with regard to matrix termination. 

Two new NAND device-only pins are added to each NAND package. One pin is an input (En_In) and the other an output only (En_Out). These pins are connected to configure the NAND packages in a daisy chain. At initialization, only the first package in the daisy chain will accept a volume address assignment. After the first package has an assigned volume address, the En_Out pin will be pulled HIGH, allowing the second package to accept volume assignment. This sequence will continue until all packages that share the same CE_n pin have unique volume addresses. At that point, the host controller has the ability to address packages, whereas with prior architectures, a separate CE_n was required (Figure 5).

Figure 5
Implementing CE_n reduction: A single CE_n signal is shared across several NAND packages. The ENi and ENo signals are connected in daisy chain, allowing only one package at a time to be appointed a unique volume address at initialization.

The ONFI 3.0 NV-DDR2 interface provides the features required to achieve 400 MT/s on the NAND interface. While Toggle Mode 2.0 can serve as a compatible alternative, the ONFI NV-DDR2 interface offers additional features that add flexibility and cost reduction. Work is ongoing in an ONFI-JEDEC Joint Task Group to achieve a common 400 MT/s interface. 

Micron Technology

Boise, ID.

(208) 368-4000.

[www.micron.com].