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Digital I/O Module on PXI Basis for Signal-Critical Applications

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Two JTAG Digital I/O Modules on PXI bus basis support structural JTAG/Boundary Scan tests as well as dynamic I/O operations up to 100 MHz for functional test executions. The  PXI5396-DT/x modules from Goepel Electronic feature an impedance controlled VPC interface for direct coupling to signal-critical load boards or other verification environments. Consequently, users are now able to utilize only one piece of test hardware for both laboratory verification and in the production line with fixture-based systems, which results in a significantly higher flexibility.

The PXI 5396-DT/x modules are based on a two-component solution, consisting of a PXI supported interface module (IFM) and an offset desktop module. The modules can be separated as far as 2 meters without loss of performance. The desktop module is equipped with a front connector developed by Virginia Panel Corporation, which allows the module to be connected directly to the test environment. Due to this, an optimum reliability of the I/O signals is achieved by fully controllable line impedance.

Two variants are available, which differ in the onboard memory depth of 72 Mbyte with the PXI 5396-DT and 144 Mbyte with the PXI 5396-DT/XM. Both variants provide 96 single-ended channels, configurable as input, output and tri-state, which allow simultaneous driving and measuring, as well as real-time comparison. While the signals are processed synchronously to the test bus operations in the JTAG mode, the dynamic I/O mode allows functional testing with freely programmable clock rates within the range of 500 Hz to 100 MHz. Hence, structural boundary scan tests with succeeding functional tests can be executed with the same instrument.

The included VarioCore technology adds extra flexibility to the module by enabling the use of custom IP embedded in the module hardware. Both PXI 5396/FXT-x are fully software-supported by the integrated JTAG/Boundary Scan development environment System Cascon from version 4.5 on. This includes the automatic generation of wiring diagrams, as well as the automatic test program generation (ATPG) for boundary scan. After the test is finished, a failure diagnosis on pin and net level is executed, with the fault location being visualized in the layout.

The execution of functional dynamic tests and the subsequent failure diagnosis are based on the support of the standard IEEE 1445 Digital Test Interchange Format (DTIF), which is now integrated in System Cascon. Additional to the import processors, an interactive waveform editor is also available.

GOEPEL Electronic, Jena, Germany. +49-3641-6896-739 [www.goepel.com].