TECHNOLOGY IN SYSTEMS
Power Management--Making Every Electron Count
Software Considerations to Manage and Optimize System Power
Modern CPUs have rich facilities for power management. The combination of a power-aware RTOS with application-level strategies can enable designers to greatly optimize system-level power consumption.
ADAM KAISER AND ARVIND RAGHURAMAN, MENTOR GRAPHICS
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A pervasive trend in the embedded space today is the constant and unrelenting demand for end-device functionality. The advent of 32-bit micro-controllers (MCUs) such as those based on ARM Cortex M series, MIPS MIPS32 4K-class cores, etc., have drastically increased the processing power and functionality available to MCU-based system designs. In addition, today’s MCUs offer a rich set of peripherals that enable enhanced features such as network connectivity and advanced human-machine interfaces (HMI). These developments have enabled system designers to create new and exciting applications with increased functionality and improved end-user experience.
While all of this is good news, developers still face challenges when it comes to managing system-wide power consumption and optimizing designs for power efficiency. Heat dissipation constraints and battery life requirements impose tight power budgets on portable device designs. In addition, “green thinking” and the environmental impact of a device’s power consumption have become important considerations across the industry. It’s imperative that system developers have a good understanding of the power management capabilities of the underlying MCU and the facilities available to them in order to effectively manage and optimize device power consumption.
Silicon vendors have made significant improvements in semiconductor design and fabrication processes to reduce MCU power consumption. Component miniaturization (i.e., shrinking a design) and lowering of the internal operating voltage levels have resulted in significant power savings. Innovative IC design techniques provide various architectural facilities that enable a system designer to effectively manage/optimize MCU power consumption. Modern day MCUs, such as the Texas Instruments Stellaris family of micro-controllers, provide distinct power domains within the MCU to enable low-power operating modes.
The availability of multiple power modes allows developers to switch the system to lower power during periods of inactivity. Some architectures even integrate hibernate blocks with a voltage domain that is completely independent from the rest of the microcontroller. These hibernate blocks enable very low power consumption by including only the minimum number of gates required to keep the system “breathing” on a back-up battery. These include a low frequency oscillator, a real-time clock, a small amount of RAM to save state, and a wake-up mechanism to exit from hibernate mode.
In order to realize further power savings, MCU designs provide the infrastructure required for software control of power and clock to system peripherals and memory. This allows system designers to make run-time decisions to shut down sections of the MCU and memory when they are not required. In addition, MCUs also allow for software control of operating frequency and sometimes voltage. This enables developers to leverage dynamic frequency and voltage scaling techniques (DVFS) to realize power savings.
With the increased CPU performance, and enhanced network connectivity and HMI features offered by MCUs today, even simple applications have become multi-threaded systems. To coordinate operation, as well as maximize use of an MCU’s low-power architectural capabilities, systems need a power-aware, real-time operating system.
The Power-Aware RTOS
An RTOS-based system design provides two key advantages for developing power-efficient applications. First, the multi-threaded application model provides an enabling framework to switch the system to low-power operating modes during system idle time. System idle time is defined as periods of inactivity when there are no tasks/threads ready to run. Second, a power-aware RTOS equips developers with proven, well abstracted, ready-to-use APIs that enable application-level control of peripheral power states, system power states and operating voltage and frequency.
Real-time operating systems, such as the Nucleus RTOS from Mentor Graphics, provide built-in power management facilities that automatically utilize the discovered hardware power management capabilities while enabling developers to effectively manage system power consumption from the application level. Using these facilities, a system developer can effectively optimize an application’s static and dynamic power consumption.
Static power consumption in a system can be directly attributed to the number of peripheral blocks that are active—clocked and powered ON—at a given point in time. Substantial power savings can be achieved by powering OFF peripherals that are not being used. Although this sounds fairly simple, the implementation details of safely switching between peripheral power states during run-time in a multi-threaded environment can become rather complicated.
Power-aware RTOSs abstract the implementation details and enable developers to make high-level decisions on peripheral power states. For example, Nucleus provides the concept of system power states to optimize the static power consumed by a device. A system power state is a user-defined set of CPU and peripheral power states. Depending on the device usage model, the developer can define various system power states and make application level decisions to transition between them at run-time. Figure 1 shows static power measurements at various system power states (SS0—Standby, SS1—playback, SS2—User idle, and SS3—User active) for an MP3 player implementation.
Illustration of power savings achieved by system power state control.
Optimizing Dynamic Power Consumption
An application’s dynamic power consumption can be directly attributed to system activity. Many embedded applications spend most of their operating time waiting for an external event to occur, for example, waiting for a user key pad press event, waiting for idle timed-delay to expire, waiting for receipt of a data packet, etc. During such periods of low or no system activity, the low-power modes provided by the underlying MCU can be effectively utilized by the operating system to achieve run-time power savings. In addition to switching the MCU to low-power mode, other power hungry blocks present in the system can also be transitioned to low-power operating states to maximize power savings. For example, SDRAM modules can be transitioned to self-refresh mode during long periods of inactivity. Figure 2a illustrates the power savings achieved by placing CPU in idle mode and SDRAM in self-refresh mode during system idle-time.
Power savings achieved by transitioning to low-power states during CPU idle time.
Transitioning to a low-power mode has associated costs in terms of power and time to enter and exit the desired low-power mode. An OS scheduler can make intelligent decisions on the most optimal low-power mode transition based on the expected system idle time, and power cost of switching in and out of the low-power mode as compared to the expected power savings. For example, when an expected idle-time is detected in the RTOS, the scheduler invokes platform-specific CPU idle functionality, which determines if the expected idle time is greater than an empirically determined threshold. The value of this threshold is experimentally determined by performing measurements of the cost and benefits and only making the decision to go to the lower power mode if there are expected overall system power savings. Figure 2b illustrates the principle behind this determination. For longer periods of system inactivity such as when a device is in hibernation, real-time operating systems should effectively use any hibernate facilities provided by hardware to save and restore system state.
Heuristic to determine the threshold value to switch to low-power mode.
Advanced techniques, such as OS tick suppression can be used to prolong the duration of CPU idle-time, thereby multiplying the idle-time power savings that can be achieved. Typical real-time kernels use a periodic OS tick timer interrupt to evaluate the internal state and to make scheduling decisions. Tick suppression enables the kernel to dynamically change the time period of the OS tick timer interrupt based on the expected idle time. This enables the system to stay in low-power modes for longer periods of system inactivity. It is to be noted that the calculated power savings may not be fully realized if the CPU is frequently interrupted by asynchronous breaks during idle time. Figure 3 illustrates OS tick profiles with and without tick suppression enabled.
A 50x reduction in OS tick frequency during periods of system inactivity with tick suppression enabled.
Most applications require the peak processing capability of the underlying CPU for only a small percentage of its operational time. Considerable power savings can be obtained using dynamic frequency and voltage scaling (DVFS) techniques. That means scaling down the CPUs operating voltage and frequency at the cost of performance. The system developer can make application-level decisions to pick an optimal operating point, i.e., a frequency and voltage setting, depending on the device functionality required. A switch from one operating point to another requires doing the following: notify all concerned peripherals of the operating point change request, stop peripheral activity, change CPU clock, bus clocks and peripheral clocks for the new operating point, and resume CPU and peripheral activity. A power- aware RTOS should abstract these details and enable the user to make application-level DVFS decisions.
Silicon vendors are constantly developing and integrating innovative new mechanisms to optimize device power consumption. Increasing complexity and functionality of end applications, aggressive low power budgets, quality of service and performance requirements, and aggressive time-to-market pressures have made a power-aware RTOS-based design a table stake requirement for feature-rich MCU applications.