TECHNOLOGY IN CONTEXT
FPGAs Mix It Up with CPUs
FPGAs Mix It Up with CPUs – The Era of the SoC FPGA
The convergence of many factors is enabling a new class of device for the embedded arena. The SoC FPGA combines powerful multicore processing on the same device with an FPGA fabric to optimize parallelism, power consumption and performance.
CHRIS BALOUGH, ALTERA
Page 1 of 1
Semiconductor devices that integrate FPGA fabric, hardened CPU subsystems and other hardened IP—SoC FPGAs—have launched a new era that will lead to their broad proliferation in the next decade, offering many new options for system designers. These SoC FPGAs complement the decade-long availability of soft-core CPUs and other soft IP for building systems and earlier attempts at integrating hard CPUs on FPGAs. A mix of technical, business and market forces make this a tipping point, and vendors such as Altera, Cypress Semiconductor, Intel and Xilinx have announced or shipped SoC FPGA devices.
Hitting the Tipping Point for SoC FPGAs
The industry’s first decade of integrating FPGAs and CPU systems was marked by both success and failure. The initial SoC FPGAs, which featured hard CPU cores embedded in the FPGA fabric, met with limited commercial success. At the same time, the use of soft CPUs on FPGAs was broadly accepted, showing the fundamental market desire for the integration of FPGA and CPU technology. A variety of new factors is reshaping the environment, leading to a tipping point where SoC FPGAs will broadly proliferate in the market. These include basic physics and advances in process technology among other factors.
One fundamental factor involves the economics of Moore’s Law. Keeping up with Moore’s Law is becoming more expensive. Fabrication facilities that build advanced CMOS semiconductors cost approximately $6B-$10B to build. Because it costs $40M to build a new semiconductor, a semiconductor must recover $100M of gross profit to operate in a typical profitable model where 20% of revenue is spent on R&D. At typical gross margins of 50%, a firm must capture a market of $200M or more. Outside of consumer electronics, mobile handsets and PCs, there are few application markets of this size, making single-purpose, or fixed function, device investments difficult to justify.
As advanced semiconductor costs grow even more in coming process technologies, this cost structure will make it even more difficult to economically justify building fixed-function semiconductors, suggesting that programmable technologies will see increasing investment, while fixed function devices, including specialized ASSPs and CPU derivatives, will see less. Because SoC FPGAs have the potential to serve many markets, they will be the target of growing investment levels.
In the year 2000, state-of-the-art FPGAs were built on 130nm process technology, while state-of-the-art CPUs were built on 90nm process technology. Because more advanced CPUs were available, the appeal of the first generation of SoC FPGAs was somewhat dampened. Today, however, leading-edge FPGAs are targeting 28nm process technology, which relatively few commercial CPUs or ASSPs use, or are likely to use, in the near future. The process technology advantage of FPGAs significantly increases the market potential of—and the inclination of vendors to invest in—these integrated devices, as designers do not need to compromise on the CPU’s capabilities, as illustrated in Figure 1.
The divergence between primary programmable logic device technology and that used for ASICs has continued to grow.
FPGA Adoption in Embedded Systems
In the year 2000 FPGAs were still relatively expensive for most embedded systems applications, and as a result were used less frequently than their CPLD or PAL counterparts. In the last decade, however, SRAM-based FPGAs enjoyed riding the CMOS cost reduction curve, such that annual embedded surveys state that nearly 50% of embedded systems also contain FPGAs. Because one of the major appeals of SoC FPGAs is their reduced cost compared to discrete implementations, there is a large native market for silicon vendors to achieve a return on investment.
For embedded systems that already leverage programmable logic, the true value of an SoC FPGA is obvious. A critical element in the decision process is that developers who use an SoC FPGA already require programmable logic in their design. They require programmable logic for customization to create product differentiation, flexibility to support emerging standards, extend product life, and/or facilitate hardware updates in remote locations—or one of a dozen other reasons that justify the use of FPGAs today. These developers already have the tools and technical expertise to design customer hardware for FPGAs and clearly understand the benefits of this new class of device. With an SoC FPGA, system developers can bring several discrete devices, (CPUs, DSPs, peripherals for communication and household tasks, networking ICs and FPGAs) into a single chip, saving BOM costs, system board space and system power (Figure 2).
A generic example of an SoC FPGA, sometimes also known as an application services platform (ASP), shows a dual-core hard processor system with its complement of hard peripherals on the same die with an FPGA fabric.
The term embedded processing covers a broad spectrum of applications, from extremely cost-sensitive 4-bit processors, to extremely sophisticated multicore 64-bit machines. Similarly, this application breadth has long supported a widely diverse and fragmented base of processor types, operating systems and software vendors. Yet that diversity is markedly different in the year 2011 as compared to the year 2000. For all its size and variety, the overall embedded market is shifting en masse to faster and more capable processors; for example, 16-bit microcontrollers give way to 32-bit CPUs. At the same time, support for 32-bit CPU families is consolidating around four widespread architectures: ARM, MIPS, PowerPC and x86. The reason for this consolidation is due mostly to software commonality and reuse. As a result, SoC FPGAs that incorporate one of these CPU architectures can address an intrinsically larger market, thereby adding more incentive for vendors to invest in this class of semiconductor.
Processor performance is constantly improving due to architectural innovations and parallelization, providing excellent solutions for software-based elements of control and algorithmic uses. And while very high performance can be achieved by increasing processor parallelism, this comes at a cost of increased power consumption and complexity of mapping the desired function. True high performance can be achieved most efficiently by creating algorithm-specific solutions in FPGA fabric. A high-level programming language like OpenCL will support this by allowing synthesis from a high abstraction level down to optimized hardware acceleration.
The need for power efficiency is also fueling a move to parallel and multicore computing. The evolution of computing has been and will be toward higher performance. Initially pursued through increase of processor architecture efficiency and frequency, the increase in cost and power consumption of this strategy has reached a limit. Current strategies focus on parallelism, with the near-term focus on processors shifting from higher, single-core processing power toward multicore implementations. As part of this quest for higher computing performance at lower power, attention is moving toward using FPGA logic as hardware accelerators for CPUs.
A monolithic SoC FPGA system maximizes power efficiency and software partitioning flexibility. SoC FPGAs allow hundreds of data signals to connect different functional areas, thus enabling 100 gigabits per second (Gbit/s) bandwidth, or greater, with nanosecond-level latencies, representing orders of magnitude better performance and latency than discrete implementations. Furthermore, monolithic integration permits sharing of memory controllers, allowing high-bandwidth memory access for hardware accelerators.
This increased performance and memory access enables the use of the FPGA for finer-grained accelerators to address a broad class of computing requirements. Because hardware accelerators can have more than 1,000 times the power efficiency of CPUs, designing for SoC FPGAs creates significant potential for an improved approach to power-efficient computing, beyond what simple multicore parallelism can achieve.
To simplify implementation of accelerators, parallel programming languages that support cross-platform, parallel programming of heterogeneous systems, such as OpenCL, are gaining in popularity. Using OpenCL as a framework for parallel programming allows users to synthesize at a high abstraction level, very efficient data paths and compute elements with very high performance capabilities.
The Platform Effect
Products that have an adoption interrelationship between producer, user and ecosystem tend to exhibit what is called a network effect, or a platform effect. The basic tenet of the platform effect is that the more use a particular product or standard attracts, the more valuable it becomes to members of the user base and ecosystem. As a result, the members of the user base and ecosystem then invest more in the technology, thus attracting more use and creating a self-reinforcing cycle. Familiar examples include PCs, video recording formats and social networking sites.
In general, product categories that have the innate possibility to operate in a self-reinforcing cycle have a strong tendency to evolve in the cycle, as each actor in an emerging product category looks to maximize ROI. As soon as a potential platform starts to gain momentum, it begins to attract investment, and thus the market dynamic can quickly shift toward that standard.
SoC FPGAs have a strong likelihood to see this platform effect. As SoC FPGAs proliferate, there will be a strong desire for users to reuse their FPGA IP and design software know-how across a wider variety of systems. For example, members of CPU ecosystems will prefer to learn as few FPGA development tools as possible, and CPU vendors will prefer to minimize the amount of FPGA development tools and technology they need to know. As a result, an SoC FPGA platform that supports multiple vendors and CPU architectures will be best positioned to trigger this platform effect investment, thereby creating the most advantages to customers and ecosystem members who join in its adoption.
The Era of the SoC FPGA
The era of SoC FPGAs has begun. These devices have reached a tipping point driven by key economic, technical and market forces, and numerous vendors have already announced or are shipping. Executive management and system architects should carefully consider platform effect, IP reuse and FPGA process technology benefits when evaluating system solutions.
Altera has partnered with leading CPU vendors ARM, Intel and MIPS, to provide a common FPGA platform for SoC FPGA devices and soft CPU solutions. This partnership will allow the industry’s most widespread CPU architectures and their ecosystems to inherit the same advanced FPGA design flow, thereby maximizing the IP reuse and flexibility within this platform. This integrated approach creates a platform effect that will foster growth and development.
San Jose, CA.