Data Acquisition with Small Modules
Solving Data Transport Challenges in Radar and Sensor Applications
FPGAs have been shown as the ultimate guarantors of real-time performance for high-speed inter-processor and I/O communication in defense applications. It is important to select the appropriate architecture to meet performance metrics, and the appropriate development tools to meet time-to-market.
RAFEH HULAYS, PH.D, ADVANCEDIO SYSTEMS
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The military and various national security agencies use high-power radio monitors, remote surveillance, satellite imagery and radar systems to monitor and detect hostile and illegal activities before and while they unfold. Systems are deployed remotely and sensor data are backhauled to central monitoring and coordination sites for processing. Figure 1 depicts a net-centric COMINT or ELINT wideband analysis application with real-time record and playback capability. Data are being collected and backhauled to a central location from multiple sensors for analysis.
A typical high-level architecture for a network-centric signal intelligence system showing the major different elements interconnected by 10GbE networks.
Today’s high-performance signals intelligence (SIGINT) systems require massive processing power to detect, identify and classify an enormous number of highly complex signals. SIGINT systems typically consist of a variety of functional elements such as signal processors—themselves often consisting of multiple processing elements—snapshot memory buffers, high-speed data recorders and bulk storage. All these may reside in multiple physical units, connected through high-speed data pipes. In many application dataflows, the processing elements within and between the distinct units need to be interconnected using switched fabrics. Real-time Command, Control, Communications, Intelligence Surveillance and Reconnaissance (C4ISR) applications such as these have a requirement to send raw sensor data in parallel to storage and multiple processing streams—a challenge that 10 Gigabit Ethernet addresses handily.
10 Gigabit Ethernet’s (10GbE) ubiquity, performance, portability and future roadmap make it an attractive high-speed interconnect for such real-time high-bandwidth situational awareness systems. This has led some to propose the use of commercial Ethernet cards or chipsets for defense applications. Unfortunately, such systems are unable to meet the stringent requirements demanded by such applications and this results in suboptimal performance.
A robust and efficient connectivity solution to a networked signal intelligence architecture operating in real time must support high-speed point-to-point data pipes to transfer data between distinct units or chassis and high-speed networking of multiple units that need to share data with an extended duration line-rate burst. There is a requirement for a time stamping and synchronization interface to deterministically and precisely stamp packets entering or exiting.
It is necessary to provide the ability to drop in a solution out of the box or tailor the transport layer protocol offload to the application, bus interface and host processor along with the ability to alleviate CPU burden by offloading intensive application processing operations or inspecting and dropping packets that are uninteresting before they ever get to the CPU. It must also be possible to modify the standard transport protocol behavior to tag but not drop the packets received with checksum errors. The system should be available in multiple form factors to accommodate different deployment scenarios.
The choice of the User Datagram Protocol (UDP) instead of the TCP protocol was driven by the need for a low latency solution in a controlled network where packet loss is negligible. In such a network, it would be difficult to justify the higher latency resulting from the sliding window protocol used in TCP communication. In addition, retransmitting data at a 10 Gbit/s rate requires very large memory buffers on both the transmitting and receiving ends, which is both impractical and unnecessary in radar applications. In addition, memory buffers are best utilized to handle bursts of incoming data. It is therefore more efficient to use the UDP protocol, tag the packets having checksum error and allow the system architect to decide whether to drop or use them.
FPGA Technology as a Solution
AdvancedIO was the first company to introduce to the market 10GbE FPGA cards to solve the challenges encountered in data transport for sensor and radar applications. We argued that FPGAs have proven themselves in ruggedized systems and are deployed extensively in the military in some of the harshest environments. No other technology is able to match FPGA performance in processing large amount of data in real time, an essential part of radar design. It is therefore the obvious choice to underpin a robust real-time data transport solution.
The military’s need for high-quality and high-performance COTS solutions made it necessary that standard implementations be made available to perform high-efficiency UDP offload on various form factors such as XMC and PCIe. For applications demanding customization, AdvancedIO pioneered the use of FPGA development frameworks, which eases and accelerates the process of developing and customizing applications.
A development framework abstracts the details of Ethernet protocols and interfaces, memory controllers and host fabric interfaces, thereby reducing the development effort and schedule for designers to customize the transport protocol, to analyze, manipulate and route the data (Figures 2 and 3). A development framework must at minimum abstract underlying hardware interfaces and Ethernet communications protocol functions. This allows developers to focus 100 percent of their time on application development and integration rather than spending time on getting all the external interfaces working on the FPGA card. A proper development framework must ensure application portability among FPGA device families and within the same family of cards. This significantly reduces the costs of future migration or upgrade cycles.
The expressXG FPGA Development Framework developed by AdvancedIO consists of an interface wrapper and a user sandbox. The wrapper, a hardware abstraction layer, provides a robust user interface to all high-performance interfaces required for an FPGA Ethernet card to fully function. The sandbox region, where designers play, features easy-to-follow examples that will jump-start user application development and debugging. This is made available to engineers to add their own customizations and perform additional signal processing before the data is packetized and sent out to the Ethernet network.
All features are intended to function out of the box and to promote the rapid coding and integration of high-performance applications with FPGA technology. The expressXG FPGA development framework enabled the development of a highly efficient UDP/IP protocol offload engine that abstracts 10GbE communication. This enables engineers to focus on implementing their solutions without the need to worry about the nuances of 10GbE protocols.
A carrier card (or the sensor card itself) is equipped with an FPGA that communicates with a 10GbE XMC module over XAUI as per the VITA 42.6 standard. A Streaming Front End (SFE), which is a small IP core that resides on the carrier’s FPGA, provides a user interface to the 10GbE module and replaces the software device driver typically used in PCI Express implementations (Figure 4). The 10GbE module has a built-in Ethernet protocol accelerator, which performs all of the functions required for UDP/IP communication over standard 10GbE networks. It also supports multicast and broadcast, which make it suitable for communication with several processing elements. For socket setup and diagnostics, the 10GbE module supports the Internet Control Messaging Protocol (ICMP) and the Address Resolution Protocol (ARP).
The architecture of the Streamed Front End (SFE) implementation over XAUI. The sensor’s data undergoes signal processing before being sent to the Ethernet module over XAUI.
The SFE has a simplified interface so that an engineer with standard socket programming skills can be confident about integrating it within his or her application. It is lightweight so that it occupies minimal resources on the carrier board’s FPGA. This leaves plenty of room to implement complex signal processing algorithms without it having any measurable effect on system performance or cost.
Here we have presented the overall requirements for net-centric COMMINT and ELINT systems and the technologies that can help an engineer implement a robust and scalable solution. UDP on 10 Gigabit Ethernet and powered by FPGAs helps meet the challenges of today’s modern systems. There is also a method to implement efficient data streaming that substantially improves performance. In addition, a development framework is available that enables the rapid customization of the transport protocol and helps implement algorithms to exercise the sensors’ data.