Accelerating Time-to-Market Using an FPGA and Customizable SoC Methodology

FPGAs can cut the time-to-market and development expense associated with ASICs. By working with the manufacturer to private label FPGA-based designs, a customer can achieve faster turnaround, lower costs as well as increased prestige in the market.


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Today’s ASICs can take up to a year and a half to get to market. For emerging markets that are evolving, such as the smart grid, developing an ASIC makes it very difficult for a company to react nimbly to competitive pressures or evolving standards. The cost of ASIC development is also an issue that can hinder the profitability of a system unless it is an extremely high volume application with no expected functional changes that would require a new ASIC development.

Many companies have opted to mitigate this challenge by using FPGAs for development and testing before migrating to an ASIC for volume production once the design is validated. This presents other issues in addition to those above. While the functional design may be the same, the devices are not. This can incur costly and timely re-qualifications. This is especially true in applications where high reliability is critical, such as safety-critical, military and avionics markets. A comparison of approximate development timelines is shown in Figure 1.

Figure 1
As opposed to FPGA-based designs, the time to develop and verify an ASIC can be two to three times longer—even more if multiple revisions are necessary.

One way to address these challenges is through the use of a private label program such as that introduced by Microsemi. The goal of such a program is a way to rapidly bring to market economical and differentiated system-on-a-chip (SoC) solutions. Customers utilize the manufacturer’s FPGAs as privately labeled ASSPs, which allows them to get to market as much as a year or more earlier than with a standard ASIC flow. Further, it removes the expensive non-recurring engineering (NRE) costs and high minimum order quantity (MOQ) requirements associated with ASICs.

Fast Time-to-Market

Over the past decade, engineers have been using re-programmable FPGAs as the preferred prototyping platform on which to design and debug their designs. Feature creep and standard changes can be addressed prior to deployment of the device, with fast debug cycles and no waiting for silicon to return from the fab.

In order to make fast time-to-market requirements, many FPGA-prototyped designs are being delivered to the customers as proof of concept and first engineering samples. It may make sense for designs to be converted to ASICs for high volume products, but this depends on a variety of factors, including but not limited to stability and lockdown of device specifications, NREs and the product life cycle. Given the increasing ASIC development costs for advanced semiconductor geometries, many designs are often brought to market with FPGAs and then cost-reduced with subsequent newer, more advanced FPGA families. 

Large companies looking to expand and augment their product lines, as well as start-ups positioning themselves to get their foot in the door in an emerging market, are increasingly looking to FPGAs to build brand recognition as a market leader. Products carrying the company’s logo and part numbers are instrumental in end customer identification of a branded device. Devices on the PCB present the opportunity to showcase not only the key differentiating functionality but also the company reputation in building high-quality products. The combination of an FPGA programmed as an ASSP, coupled with the company’s logo, is very attractive in terms of time-to-market and brand recognition (Figure 2).

Figure 2
A private-labeled FPGA can appear with the customer’s logo and specific part number to increase the market awareness of that company’s added value.

With an ASIC, a mask revision and subsequent re-spin of a device is not always due to design changes made to address issues found while debugging during verification. Often a company’s target market and general application may have multiple customers or even multiple options or standards in an end product offering from a single vendor. The end application potentially requires limited changes internally at the device level. In this scenario, rather than spinning multiple ASICs and incurring the associated additional NREs for each incremental design, a private label solution with an FPGA not only circumvents the extra cost, but also removes the time-to-market delay, enabling new markets to be rapidly addressed with product variants. With a private label program, each variant is marked with the company’s own logo and a custom part number specific to the end application, standard or customer’s system.

Not All FPGAs Are Alike

Flash-based FPGAs go many steps forward in realizing the ability to create a secure and reliable, single monolithic IC that fits the needs of a private label program. Unlike SRAM-based FPGAs, which require a secondary EEPROM to configure the device upon boot-up, flash-based FPGAs contain all configuration data on-chip and are instant-on. From an external standpoint, the single IC solution is the first requirement of private labeling as well as the first line of defense in terms of security. In other solutions, seeing a device coupled to an EEPROM is an immediate flag that configuration data is being stored externally from the main device and the data can be intercepted during power-on. Labeling both SRAM FPGA and EEPROM is possible but impractical when listed on a company’s product catalog as a two-chip solution.

In addition to the single IC approach, flash-based FPGAs include the ability to lock the FPGA contents from being read back by competitors or unauthorized personnel. Microsemi FPGAs, for example, include FlashLock technology to lock the device with a 128-bit key, which allows the device to be unlocked and reprogrammed by providing the same key, which is valuable for secure in-system upgradeability. In addition, permanent lock is possible, which disables programming access to the part. Embedded security keys in these FPGAs provide a further level of security by preventing internal device probing. Once flash devices are programmed, they power-up in a known state. This provides for instant-on capability, which can be used for system bring-up or self-test.

Long-term availability is always a consideration, since the last thing someone wants is to design a product that will reach end-of-life during the product life cycle. Flash-based FPGAs are built on stable and known geometries that historically serve markets requiring the highest reliability coupled with product availability that stretches to decades. To this day, Microsemi continues to ship FPGAs that were designed in by customers over 20 years ago.

Stepping up to Flash FPGAs with Embedded Microcontrollers

In recent years the ARM family of microcontrollers has found favor within numerous IC platforms. By embedding a hard ARM microcontroller within an FPGA, a new family of customizable system-on-chip (cSoC) devices has been introduced. The cSoC (Figure 3) is an ideal platform on which hardware and software teams can co-develop their system portions onto a single platform IC. The cSoC has three major subgroups: processing, sense and control, programmable analog and configurable logic.

Figure 3
A configurable SoC, such as the Microsemi SmartFusion, consists of three parts—the programmable processor with its normal complement of peripherals, a programmable analog processing section and an FPGA fabric, all integrated on a single silicon die.

The combination of an embedded microcontroller and FPGA allows for architectural algorithmic trade-offs and partitioning. Consider, for instance, a multi-axis motor controller for a safety-critical application. Dual redundancy can be implemented with safety controller #1 in the ARM Cortex-M3 microcontroller and a similarly functioning algorithm implemented in the FPGA fabric as safety controller #2. The safety certification engine validates the results from both controllers for consistency and issues commands as required (Figure 4).

Figure 4
Designing dual redundancy for safety-critical applications can be accomplished on a single silicon device.

For multi-algorithmic implementations requiring high compute cycles, the computationally  intensive portions of the algorithms can be offloaded into the FPGA to perform parallel processing. The FPGA fabric can be used to implement extremely fast and efficient subroutines, thus increasing the headroom of the Cortex M3 microcontroller for performing task management application layer execution.

Preprogrammed FPGAs used in a private label program can be configured at any time. A key to good inventory management is to select a common set of density/package combinations on which to develop a complete line of private labeled devices with slight permutations of similar designs or completely different functionality. Once a customer has placed an order, the devices can be programmed and labeled in house or at the manufacturer. This option also further accelerates time-to-market by reducing manufacturing time in that this step is removed from the customer’s contract manufacturing flow.

FPGAs are continually finding usage in an assortment of applications and use models. Private labeling FPGAs as customer-defined ASSPs is an excellent step toward building differentiation and expanding product lines. This approach has many advantages, including prototyping and going to market on the same design and debugged IC platform and the removal of high barrier NRE costs. Flash FPGAs go the further step by adding additional layers of security in the form of on-chip configuration, hardware implemented security keys and instant-on usability. The latest form of flash-based cSoCs take the concept even further by allowing a platform on which to partition advanced, high value algorithms into the embedded ARM Cortex-M3 microcontroller and FPGA fabric. Fast parallel processing can be implemented to achieve aggressive processing goals while reducing power consumption when compared to conventional high frequency processing elements. 

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