SMALL FORM FACTOR FORUM
SFF Connectors Go 3G
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Each time that mainstream computer markets shift their buses and peripheral interfaces into overdrive, large trade groups and their entourage of board and connector manufacturers spin up their SPICE models and simulations, pushing further the limits of transistors, dielectrics, circuit board materials, traces, pads and pins. Subsequent room temperature validations signal the onslaught of high-stakes motherboard mass production, never looking back. Consumers and enterprise users need not ponder the feat of science underlying their eSATA, CFast, DDR3, PCI Express MiniCard (mini-PCIe), HDMI and Thunderbolt devices.
Here in our small form factor (SFF) embedded community, resources and budgets are much thinner, so we select their transceiver chips, modules and connectors wherever possible. For example, wireless modules with gold-plated card-edge fingers already went through meticulous RF design and type certification or agency compliance testing. Certainly not for the faint of heart, and why re-invent the wheel? Yet if your stack doesn’t boot your OS or run the commercial market Wi-Fi and flash components that you want to use, you must iterate your design until it does. You’re not going to convince those suppliers to modify their mass-market modems and media for your modest means.
Desktop, laptop and tablet motherboards are spacious enough to include all needed circuit components. But many SFF systems need custom (non-consumer) I/O and tinier underlying system footprints, gladly sacrificing height for girth. Therein lies the rub. So much for the convenience of taming the wild high-speed signals on just a single board. Going off-board completely re-opens all of the original SPICE models and simulations.
Without the luxury of well-oiled standards groups and connector design teams firing on all cylinders, the many factions of the SFF world might have a hard time even figuring out where to start. Computer-on-module (COM) and mezzanine card manufacturers only have to worry about high-speed signals going off a board once or twice. Stackable CPU and I/O architectures, meanwhile, must design for many more off-board transitions. Truly shrinking a system means reducing or eliminating unused internal connectors and buses.
For mezzanines and COMs, signal integrity across the gold fingers appears to be adequate for second-generation PCIe, SATA, LAN and USB waveforms. The board manufacturers are off the hook for now. Luckily, several connector manufacturers have introduced a third generation or “3G” of embedded-focused connectors to handle these signals in the more demanding stackable environments. Whereas connectors that accept gold-flash-plated card edges are designed to minimize computer height (thickness), these embedded stackable connectors allow tall components between circuit boards—essential in converting wide flat consumer profiles into tall slender stacked figures.
There are real physics and engineering disciplines behind maintaining the characteristic impedances (single-ended and differential) across a large 0.6” to 0.8” air gap between fiberglass boards. Contacts shaped for sufficient wipe length for good airtight connection must also have dimensions that hold the impedances within tight tolerances to minimize signal reflections, insertion loss, return loss and near- and far-end crosstalk. Add embedded operating temperature ranges to the recipe. Not your basic cup of tea. Eye diagrams show whether the rising and falling voltage swing happens in a short enough time span; the receiver is the beholder whose eyes don’t lie. Connectors with ground “blades” up the center between rows of pins are integral to the crosstalk and impedance performance, with a side benefit of knocking down EMI and handling DC current return paths as well.
Modular tooling designs create several versions with different “banks” of pins, making it easy for standards groups to define scalable solutions from entry level / low cost (PCIe and USB), all the way up to high bandwidth (more Express lanes plus SATA). Using ground blades, even PCIe 3.0 transmit, receive and clock signals can be passed up through multiple board + connector sets.
Another style of 3G SFF connector is a pin field / array mated pair. This connector is shorter and wider—a welcome trade-off for certain tiny SFF boards—by expanding to 4, 5 or 6 rows of 40 or 50 pins each. Board designers have more flexibility with signal-to-ground ratio. Multiple stack height options are available for this style as well, to dial in the optimum three-dimensional space occupied by the board stack. Connector manufacturers and standards groups focus on this market, upshifting SFF systems to high-performance interconnects using both off-the-shelf and custom CPUs and I/O cards.
Connector vendors in the SFF space don’t exactly race out to tool up a new molded connector. We can thank the decades-old logic analyzer heritage for today’s stackable-ready 3G connectors. We show gratitude by using these connectors in upgrades and next-generation systems.