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Next-Generation Design Suite Accelerates Time to Implementation from C and RTL

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Xilinx has made available its next-generation design environment. The Vivado Design Suite 2012.2 is now available at no additional cost to all ISE Design Suite customers who are currently in warranty. This release is the first in a two-phase rollout, with the first phase focused on accelerating time to implementation from C and RTL, and the second focused on accelerating time to integration of system-level functions. Vivado Design Suite 2012.2 delivers a highly Integrated Design Environment (IDE) with a completely new generation of system-to-IC tools that include High-Level Synthesis, RTL Synthesis with SystemVerilog support, analytical place and route, and an advanced SDC-based timing engine so developers can increase their productivity with a 4x acceleration in design implementation. 

The Vivado Design Suite 2012.2 place and route technology accelerates implementation cycles by using analytical techniques to optimize for multiple and concurrent design metrics, such as congestion, total wire length and timing. For complex designs, this results in performance improvements of 15 percent corresponding to a 1 speed grade advantage over the ISE Design Suite.

With the general release of the Vivado Design Suite, Xilinx is releasing Vivado High-Level Synthesis (HLS) for All Programmable 7 series FPGA and Zynq-7000 EPP SoC devices. Designers can quickly explore implementation architectures for complex algorithms by synthesizing their C, C++ or System C code to RTL. Vivado HLS also integrates with the System Generator tool by creating fast simulation models for enabling the rapid development of applications such as video, imaging, RADAR and baseband radios. Not only does Vivado HLS accelerate algorithm implementation, it also reduces verification time by up to 10,000x while improving system performance by enabling RTL micro-architecture exploration. 

To further accelerate designer productivity, Xilinx continues its on-going collaboration with its growing base of key Xilinx Alliance Program members by ensuring IP cores are validated and design tools are available to augment the ISE Design Suite and Vivado Design Suite tools. This collaboration is also key for the second phase of the Vivado Design Suite rollout that includes the Vivado IP Integrator, an interactive design and verification environment, and the Vivado IP Packager, which enables Xilinx, third-party IP providers and end customers to package a core, module or completed design with all constraints, test benches and documentation. 

Xilinx, San Jose, CA. (408) 559-7778. [www.xilinx.com].