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JTAG Boundary Scan Tester/Programmer Relieves Users of Detailed Setup

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A Universal JTAG Boundary Scan Tester and Programmer can be utilized as a production run time and application development system for performing circuit card assembly (CCA) structural integrity tests or CCA programming. The available assets packaged within a small footprint make the JTS1000 from JTAG Technologies suitable for both Production and Field Testing. The JTS1000 utilizes Astronics DME’s Test EZ Software Suite for automated testing and program development. 

Other standard features include:

  • Stand-alone bench-top LXI-based system
  • JTAG TAPS with up to 256 programmable digital I/O channels 
  • 6.5 digit DMM
  • Power and multiplexed switching
  • 16-port Ethernet switch
  • Up to 4 programmable DC power supplies
  • Plus various software 

JTAG Technologies recently introduced high-level JTAG access routines, which can be linked into the Python freeware open-source language. Called JTAG Functional Test (JFT) routines, they work at two levels (or perspectives), namely: boundary-scan pin-level and “cluster” pin-level.

In the boundary-scan pin-level scenario users can set up tests with minimal knowledge of the interconnections and without reference to a design netlist. Individual pins can be driven using DriveHigh, DriveLow and HighZ, and individual pins can be read using TestHigh and TestLow.

Also, groups of pins can be defined by DeclareGroup. For example, the pins of a JTAG-compliant device that connect to a (non-JTAG-compliant) DAC might be grouped and named “DAC-input.” The variable DAC-input can then be controlled using a DriveVar command. Similarly, the output of an ADC could be suitably named and read by a TestVar routine.

Using JFT at this level allows design engineers to undertake debug sessions without the need to create specific test firmware or FPGA test configurations. Equally, repair or service personnel can easily create test scripts to cover well-known fault signatures. The cluster pin-level perspective takes testing to the next level/stage by allowing the user to specify pin-level and variable-level drives—testing from the device under test’s (DUT’s) point of view.

JTAG Technologies, Mission Viejo, CA. (949) 454-9040. [www.jtag.com].