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Space-Qualified, Low-Power SBC Offers 1.0 GHz Processing

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A space-qualified, radiation-tolerant 3U CompactPCI SBC performs with an exceptionally low power of only 10W for manned spacecraft and unmanned satellite subsystems and platforms.  The SP0 from Aitech Defense Systems, based on the compact MPC8548E PowerQUICC-III PowerPC, can achieve a processing speed of 1.17 GHz and 333.3 MHz of core complex bus (CCB) and DDR-1 memory speeds, while adhering to the low power and small form factor requirements necessary in most satellite and spacecraft, mission-critical applications.  

The SP0’s processor includes an e500 System-on-Chip (SoC) integrating both an L1 cache with 32 Kbyte instruction and 32 Kbyte data and a 512 Kbyte L2 cache. A large user Flash of 1 Gbyte is standard, with the option to expand up to 8 Gbyte. Supporting both processor and application needs, the large onboard memory also includes up to 512 Mbyte of fast DDR1 SDRAM with ECC protection for high data integrity as well as 512 Kbyte of redundant Boot Flash.

The SP0 includes two Gigabit Ethernet ports, four asynchronous, high-speed serial communications ports and up to five general purpose discrete I/O channels—and more. An included industry-standard PMC slot, either air- or conduction-cooled, accommodates additional modules and onboard functionality. In addition, up to eight PCI Express lanes or four Serial RapidIO lanes as well as dual PCI buses, further help increase onboard high performance and exceptional functionality.

When operating as a system controller, instead of as a peripheral card, the new SP0 supports up to seven additional cards on the PCI backplane complete with clock signals and interrupt and arbitration support.  

Three watchdog timers on the SP0 offer exceptional system safety parameters and reliability. One watch dog timer, located within the SoC processor, generates an internal CPU interrupt to alert the application of a pending fault. After the first timer expires and then the second timer expires, a non-maskable hardware reset is performed, which also resets the entire board. Located in the onboard FPGA, the third timer can reset the whole board or only certain I/O devices after the expiration period.  

A 1 PPS (pulse per second) timer provides a critical system backplane and external heartbeat for synchronization to other autonomous computing and communications subsystems on the satellite bus or spacecraft platform.

Aitech Defense Systems, Chatsworth, CA. (818) 700-2000. [www.rugged.com].