TECHNOLOGY IN SYSTEMS
Intelligent Sensors in Intelligent Applications
Building Power Efficient, Context-Aware Mobile Systems
The availability of a wide-range of low-cost, small-footprint sensors promises to bring a rich variety of exciting new context-aware applications to mobile systems across a wide range of medical, industrial, scientific and commercial applications.
BY JOY WRIGLEY, LATTICE SEMICONDUCTOR
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Take a quick look at the latest generation of smartphones from leading manufacturers and one conclusion quickly becomes apparent. Designers are continuing to add new levels of intelligence in highly creative ways.
Two factors are driving current innovation. One is the rising proliferation of low-cost sensors. Significant advances by MEMS manufacturers are helping drive down sensor cost and footprint. The second is the smartphone designers’ ability to develop new “context-aware” subsystems that allow mobile devices to make advanced, task-enhancing decisions without prompting the user. This revolution arguably began when leading cell phone makers began embedding proximity sensors to extend battery life and accelerometers, gyros and magnetometers to support location-based services. But today’s sensor-based context-aware subsystems go well beyond those capabilities and mimic in many aspects how humans analyze situational context.
For example, precision image sensors and ambient light sensors boost image resolution and display readability as environmental conditions change. Chemical analyzers simulate human smell awareness. Pressure, temperature, chemical and infrared sensors can measure a smartphone user’s health and help evaluate safety risks. And more sensor-based, “context-aware” applications are clearly coming. Don’t be surprised if smartphones in the very near future feature heart monitors and perspiration detectors to track user health, excitement level and mood.
Fast and Power Efficient
To make effective use of all this sensor data and optimize decision-making, however, today’s mobile systems must integrate and analyze multiple streams of data as quickly as possible. The faster data is collected from the sensors and processed into usable information, the more accurate the system’s response will be to current environmental conditions. Moreover, since these “context-aware” sensor-based subsystems are always on, they present a potentially significant drain on system power. Accordingly, these tasks must be performed as efficiently as possible from a system power perspective.
Mobile system architects can employ any of three design strategies to address this problem. They can use their system’s core applications processor to manage sensor data. They can offload the task to a discrete microcontroller (MCU) to manage the task. Or they can build an integrated sensor hub using an ultra-low-density (ULD) field programmable gate array (FPGA) to support the application processor in the same way.
Each approach offers its own benefits and liabilities. Designers interfacing each sensor directly to the application processor can take advantage of a proven architecture that leverages existing system resources. But as the number of sensors continues to escalate, designers will inevitably run into limited GPIO resources. Over the long run that restriction may threaten the designer’s ability to implement important new functions. At the same time the interface limitations inherent in any fixed-silicon MCU restrict design flexibility. Each sensor brings specific interface requirements. Some feature industry standard interfaces; others employ proprietary solutions. Meeting future sensor interface needs in a single application processor or MCU can increase design complexity and sometimes extend the product development cycle.
Perhaps most importantly, the effects of a multi-sensor architecture on a typical interrupt-driven application processor pose severe new power demands, particularly given the always-on nature of today’s context-aware sensor subsystems. The continuous collection of time-sensitive data from a growing number of sensors forces the application processor to remain operational longer and places additional demands on a mobile system’s already tight power budget.
In many of these emerging, always-on, context-aware applications, a better option lies in using an ultra-low-density (ULD) FPGA specifically optimized for mobile applications. Unlike traditional large, expensive FPGAs, this new class of device comes in low gate-count densities housed in highly compact CSP-class packaging. Yet they offer the logic resources needed to support sensor management and pre-processing functions and can be manufactured in high volume to take advantage of economies of scale.
This design approach is particularly attractive in context-aware applications, which by definition must be always on, because it allows system designers to limit the runtime of the relatively power-hungry interrupt-driven applications processor. With a ULD FPGA, designers can collect information from multiple sensors in parallel and in real time at a significantly lower clock rate than a traditional application processor or MCU. Consuming less than 1 mW, these ICs dramatically reduce power consumption compared to traditional approaches while collecting data from each sensor at near-zero latency for more accurate system response to changing environmental conditions. This further allows the application processor to stay in sleep mode longer or, if necessary, be periodically active in the lower power states. This approach of offloading time-critical sensor functions to the ULD FPGA improves both the overall power consumption as well as sensor system accuracy (Figure 1).
Relative power consumption of three different sensor hub implementations.
Moreover, as the number of sensors in mobile systems continues to grow, the footprint advantages of a ULD, FPGA-based solution prove increasingly attractive. The IR subsystem in Figure 2 offers an excellent case in point. The discrete solution on the left combines a 2 mm x 2 mm IR remote IC with a RGB LED driver that measures 2.5 mm x 2.5 mm. The total area of the solution occupies 10.25 mm2. As an alternative, designers can implement the same subsystem in an ultra-low-density iCE40LP FPGA that measures 1.40 mm x 1.48 mm or about 2 mm2. The programmable solution reduces the board footprint by approximately 80 percent, while offering more functionality by combining an IR remote block, barcode emulator, LED driver and custom algorithms.
Comparing the footprint requirements of a discrete vs. a programmable IR subsystem.
Processor versus ULD FPGA Power Comparison: The Pedometer Test Case
To measure and quantify these differences, engineers at Lattice Semiconductor recently constructed a pedometer sensor management demo system using an iCE40LM 4K ULD FPGA. The demo brought together Qualcomm’s Snapdragon evaluation board and SDK with a smartphone display. To represent a multi-sensor, battery-powered mobile application, the demo added a sensor daughtercard developed by Lattice Semiconductor.
Figure 3 shows the compact, highly integrated daughter card. Near the center of the board lies the iCE40LM 4K ULD FPGA housed in a small 25WLCSP package. The FPGA combines 4K gates of logic with a wide variety of embedded IP in the form of hard silicon blocks including two SPI master/slaves, two I2C master/slaves, a PLL, a low-power strobe generator that operates in the kHz range and a high-frequency strobe generator that runs in the MHz range. It also features RGB/LED drivers. As the photo shows, the compact daughtercard features a wide range of sensors including humidity, temperature, Hall Effect, ambient light, proximity, barometer, accelerometer, gyroscope, compass and IR transmitter and receiver.
As part of the demo system, this highly integrated daughter card combines up to ten sensors with an iCE40LM 4K ULD FPGA.
To simplify the demonstration of the iCE40LM’s sensor management capabilities, Lattice engineers chose a pedometer application that uses a single sensor, an LSM330 DLC accelerometer, to measure movement. As Figure 4 indicates, the hard IP blocks embedded in the FPGA dramatically simplified system design. The LSM330 DLC accelerometer interfaced to the iCE40LM through one of the FPGA’s embedded I2C master blocks. The FPGA also housed sensor-specific configuration logic and the step detect function logic as well the application processor’s interrupt logic. In this application these circuits dictate how often or in how many steps the FPGA wakes up the application processor and loads information. The FPGA interfaced to the application processor through one of its two embedded, fixed-silicon SPI master/slave interfaces.
Pedometer application using an iCE40LM ULD FPGA.
Figure 5 shows the system set up. The green meter on the left, measuring amps, tracked current drain for the entire system. With the display on and the applications processor awake, the meter measured 720 mA. Next, engineers put the applications processor to sleep with the system display showing 0 steps on the pedometer. System current dropped to 520 mA while system power was measured at 160 mW.
System setup for pedometer demonstration.
IAPQ8060 = 720 mA – 520 mA = 200 mA
PAPQ8060 = 200 mA * 0.8V = 0.160 W
Of course context-aware sensor applications are, by their nature, always on. So with 0 steps on the pedometer, the red meter measured the iCE40LM sensor manager at 732 µA while the applications processor was in sleep mode.
To mimic walking with the pedometer, engineers swung the sensor daughtercard back and forth. Data was collected by the iCE40LM FPGA from the accelerometer through its I2C port where it was processed in the FPGA’s sensor-specific control. As part of this process, sensor management and pre-processing functions analyzed the bitstream to evaluate how to parse the data and translate the acquired sensor data into steps. Finally the information was loaded into the accelerometer’s FIFO in preparation for the reawakening of the application processor and display. During this process the highest reading recorded on the red meter measuring the FPGA power draw was 737 µA.
At this point engineers powered the system up and initiated the application processor and system screen by pressing the wake-up interrupt. As system current increased, the applications processor turned on and queried the FIFO in the iCE40LM to ask for the number of steps recorded by the accelerometer. The data was transferred and the application processor calculated distance traveled, calories consumed and displayed the results on the system screen (Figure 6).
Once data is collected from the accelerometer, it is passed through the I2C port, processed through the accelerometer’s sensor-specific control, and loaded into a FIFO in preparation for the applications processor to turn on and display results.
A quick review of the pedometer demo results illustrates the significant power savings a ULD FPGA-based sensor management subsystem can offer. During the walking demo the iCE40LM consumed at its peak 0.737 mA * 1.2V or 0.88 mW total. That represents approximately 180 times less power than the application processor would have consumed (160 mW) to perform the same task. Given the always-on nature of context-aware sensor applications, the use of a ULD FPGA-based sensor management system that consumes less than 1 mW, particularly when spread across multiple sensor applications, would clearly extend mobile system battery life.
Moreover, the iCE40LM-based sensor management system, occupying a meager 1.7 mm x 1.7 mm footprint, offers designers highly attractive board space savings compared to alternative design options. In addition, its ability to collect sensor data in real time at near-zero latency, unlike an interrupt-driven application or microprocessor, improves data integrity and system fidelity. Finally, the use of a programmable solution that allows the designer to reconfigure I/Os and protocols, as well as optimize the size, configuration and capabilities of each sensor’s FIFO, register and arbiter, offers a level of design flexibility that other design approaches cannot match.
ULD FPGA versus Microcontroller
Next, the engineering team compared the performance and power characteristics of a discrete MCU sensor management system with the ULD FPGA-based alternative. The team began by implementing a 16-bit RISC-based MCU architecture widely used in mobile applications in the iCE40LM 4K FPGA. As a common benchmark, both the 16-bit MCU and the iCE40LM 4K FPGA were tested during I2C polling—a common function for an “always-on” sensor hub. Both devices were tested using the minimum logic necessary to configure and read the accelerometer at 20 Hz. During the I2C polling function, the iCE40LM 4K consumed 0.538 mW. Power dropped even further to just 418 µW while performing the pedometer application. Toggling between active and low power mode during I2C polling, the MCU solution dissipated approximately 3X as much power as the iCE40LM.
The test also produced some insight into the ability of each solution to detect changes in sensor data. The iCE40LM4K-based solution running at a slow 6 MHz with the I2C interface running at 400 kHz was able to collect 50 samples/s from the accelerometer. The 16-bit MCU running at a faster 8 MHz with the I2C interface running at 110 kHz could only collect 25 samples/s or half the data. The ability of the iCE40KM4K solution to operate with far less latency gives the system a better ability to detect changes in the sensor and react to them more quickly. Ultimately that near real-time response translates into a better user experience.
As mobile system designers implement these new capabilities, one of the primary challenges they will face is how to most efficiently process the data collected by these sensors. Leveraging a low-power silicon architecture and innovative packaging technologies, Lattice Semiconductor’s ULD FPGAs offer mobile system designers the opportunity to cost-effectively bring an exciting new class of context-aware functions to next generation mobile systems while minimizing system power and footprint.