FPGAs Provide Glue Alternatives


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Where would we be without programmable logic? In dire straits, certainly. Imagine bulky, slow and rigidly defined systems that need to be overhauled even for minor changes. Many everyday functions are best implemented in field programmable gate arrays (FPGAs). These chips are popular across nearly all embedded market segments, from communications to military to medical. Once relegated to simple glue logic, data acquisition and decoding functions, FPGAs now handle heavy signal processing algorithms, encryption and transforms in hardware rather than software. In some cases, even the need for a discrete DSP has disappeared.

The programmability of these devices, even out in the namesake “field,” adds tremendous value to embedded systems, whether for optimization, fixes, or the implementation of brand new algorithms. On-chip static RAM adds another full dimension of circuitry that can be implemented in a soft or firm way. Flip-flops to full memory functionality combine with very flexible routing (interconnects) and logic blocks to produce basic custom state machines and processors, giving high-end microcontrollers a run for their money.

Speaking of processors, many FPGA models come with full 32-bit CPU cores implemented in hardened IP blocks, or soft (changeable) gate-level synthesized processor blocks as well. Other I/O and IP blocks are sometimes implemented in hardened transistor circuits, improving the overall speed and shrinking die size without sacrificing much of the flexibility. Certain FPGAs start to get application-specific, almost like the ASICs and application-specific standard products that are worth replacing for time and development cost reasons. FPGAs reduce system size and weight. Power and per-unit cost may get sacrificed in the process, but often there is no other straightforward way to implement the desired functions.

One design challenge that pops up (hopefully anticipated prior to proto bring-up) is the time required for the programmable device to load its configuration from the external non-volatile storage device (a small 8-pin SPI bus chip, for example). So many bits need to be loaded sequentially. The device is essentially lifeless prior to that, and will not enumerate properly as a peripheral on a host processor’s bus yet. If the processor doesn’t stop and wait, the I/O won’t be visible and its device driver won’t be loaded. Either some polling or handshaking needs to be designed in, or the entire processor needs to be held in reset until the FPGA loads its brains.

FPGAs moved into the high-speed serial interface era with SERDES PHYs that directly attach to differential pair topologies like PCI Express and others. These ports can be ganged together to form wide high-bandwidth links, such as PCIe x4, and run at Gen 2 speeds as well. Fat pipe applications such as image processing can be handled with modest CPU horsepower and high I/O bandwidth in this manner, using Atom, Celeron and AMD G-series processors. It’s no longer necessary to choose a high-end embedded processor to get a x4 link; the x1 lanes can be merged using firmware settings.

Having a large number of I/O pins (balls) makes it straightforward to create parallel interfaces to A/D circuits for data acquisition, for example. FPGAs can provide a hub by bringing many low-speed buses into a central location, where data can be crunched and routed back out. Much of the character of the I/O is embodied within the programmable device itself, as device drivers read and write registers.

FPGAs start out assigned to particular functions. Once the design is essentially complete, they offer a chance to reduce component count by swallowing some leftover odds and ends. This saves space and cost, more so since contract manufacturers charge per component insertion. Power management signals, system control signals, handshaking lines, counters, timers, delay circuits, decoders, synchronization, FIFO buffers and other assorted glue logic can be absorbed into the same FPGA(s). While often getting upstaged by microprocessors, these sophisticated logic devices shrink and hold together all of the various subsystems, putting the “small” into Small Form Factors (SFFs).