Building out the Smart Grid

Microcontrollers Ease the Design of Solar Micro Inverters

Designers frequently encounter challenges when creating solar micro inverters based on embedded processors. A number of these can be explained by way of insight into power stage design and control.


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Solar micro inverters are a quickly growing segment of the solar power industry that is transforming design processes as we know them. Instead of connecting all solar panels in an installation through a central inverter, solar micro inverter systems place smaller, or “micro,” inverters in line with each individual solar panel. There are many benefits of using solar micro inverters, including the improvement in efficiency under partial shading conditions, improved reliability and greater modularity. However, they can be extremely challenging to design. The controller must use complex algorithms to control the power stage, synchronize with the grid using software phase locked loop (SPLL) and track to the maximum power point of the panel. I t must also execute complex state machines, which increase the computational load on the embedded processor.

The solar panel, or photovoltaic (PV) panel, as it is also commonly known, is a DC source with nonlinear voltage (V) versus current (I) characteristics. Some major challenges in PV inverter system design are extracting as much possible power from the panel by operating it at the maximum power point (MPP), as well as converting the power efficiently, allowing a clean current to be fed into the grid. A typical PV grid tied inverter consists of a string of PV panels tied together to a single inverter stage; these are called string inverters. Since these systems are not able to track to the MPP under partial shading conditions, attention and preparation are needed when installing these types of inverters. An emerging standard involves using inverters dedicated to each individual PV panel, also called micro inverters. These inverters ease the constraints on installation, and because dedicated MPP tracking (MPPT) can be performed through each panel, the system efficiency increases.

Solar Micro Inverter Hardware Design

Typical panels provide an output between 20 and 40V. This voltage must be boosted to approximately 320-400V and then inverted to feed current into the grid. Thus, a typical solar micro inverter has two stages: a DC-DC stage and a DC-AC stage, as shown in Figure 1.

Figure 1
PV grid-tied inverter for each panel has a DC-DC stage and a DC-AC stage.

Several solutions are available to ease the design of solar power systems. One solution used specifically for those developing solar micro inverters is the C2000 Solar Micro Inverter Development Kit from Texas Instruments (TI). This kit integrates a high gain clamped flyback stage, switching at 100 KHz to boost the voltage from the panel to a bus voltage for the inverter. The clamped flyback stage is used to reduce the voltage stresses on the MOSFETs. Due to the high gain in the power stage, small changes in the pulse width modulation (PWM) duty affect the output voltage by a large amount. Hence, the effective PWM resolution is reduced whereas the ADC resolution remains unchanged as the control for MPPT works on the input.

The resolution of the PWM must be greater than the ADC to avoid limit cycle behavior, which is why TI’s C2000 Piccolo TMS320F28035 microcontroller (MCU) integrates a high-resolution PWM module. This module enables the effective number of bits for the PWM to be more than what the central processing unit (CPU) clock can provide for the given switching frequency. Additionally, the panel must be isolated from the grid to adhere to strict utility requirements. Transformer size is inversely related to the frequency of operation, and thus the trend is to use higher switching frequency for the power stage to achieve compact isolation of the panel from the grid. A schematic of the power stages on a solar micro inverter kit is provided in Figure 2.

Figure 2
TI Solar Micro Inverter Development Kit power stage diagram

To avoid issues with ground current faults, a grid clamped inverter stage is used to link to the grid. The switched current from the inverter is filtered using an output filter. The filter affects the quality of the current injected into the grid, and hence it must be designed carefully. The output filter can be designed using just an inductor (L), an inductor and capacitor (LC), or an inductor capacitor inductor (LCL) combination. LCL filter increases the complexity of the control because it has inherent resonance that can be detrimental to the stability of the inverter. However, it is often preferred as it can reduce the total size of the output filter.

Resonance in the LCL filter can be damped using passive damping. This is done by adding power resistors in the filter structure. However, this results in reduced efficiency. Alternatively, active damping solutions involve using additional sensors such as those that measure capacitor current, which increases system cost. A complex pole zero pair in the compensator can be used to damp the resonance as well, though this increases the compensator complexity. This approach is preferred as it enables use of LCL filter without adding passive damping, which reduces efficiency and does not entail using additional sensors, and modern MCUs can easily manage the increased complexity of the controller.

Control and Software Design

Implementing the control loops of multiple power stages as well as implementing the algorithms necessary for grid connection and MPPT can consume substantial CPU bandwidth. TI’s C2000 MCU solar software library offers optimized functions (assembly optimized where applicable) for executing the key blocks used in the PV inverter control in fixed- and floating-point format. The blocks include an adjustable notch filter, which is used to eliminate any impacts of AC power ripple on the control variables. Compensators such as two-pole two-zero (2p2z) and three-pole three-zero (3p3z) compute the effort based on reference and feedback. SPLL locks in the grid phase, MPPT algorithm and power monitoring. In addition to the control loops, it’s also important to implement a state machine in order to start the inverter. Figure 3 shows a high-level control diagram of a solar micro inverter.

Figure 3
Control diagram of a PV micro inverter.

The current compensator must be designed with a high bandwidth because the goal of the PV inverter is to feed a clean current into the grid. Figure 4 illustrates the current control diagram for a grid connected inverter.

Figure 4
Feedback linearization for inverter current control loop

Due to grid voltage variations, the current compensator loop is subject to disturbances. A typical PI compensator is not able to track to the reference current with zero steady state error, so the effects of grid voltage disturbance must be taken into account. This is achieved by first assuming the current compensator bandwidth is significantly higher than the grid voltage frequency and linearizing the feedback. Therefore, the current compensator is thought of as generating the reference across the LCL filter and the actual duty cycle computed for the inverter voltage using the formula:

Where D is the inverter duty cycle, VDC the DC bus voltage, v8 is the grid voltage, i*g is the inverter current reference, ig is the inverter current reference, VLCL is the voltage across the LCL filter, Gp is the plant model of the LCL filter, Gc is the current compensator used and vi is the averaged inverter output voltage.

Conclusion and results

Figure 5 shows the frequency response of the closed current loop, which includes the damping of the LCL filter and the feasibility of high bandwidth as a result of the feedback linearization. Figure 6(a) displays steady state voltage and current of the micro inverter and highlights good power factor achieved and total harmonic distortion (THD). Figure 6(b) shows the starting and stopping sequence of the inverter by displaying the inverter current and panel current as the micro inverter sequences through the state machine.

Figure 5
Closed loop inverter current frequency response.

Designing embedded solar inverters can pose a challenge to designers. To help mitigate common challenges, this article has presented various reasons for power stage selection, identified the need for high-resolution PWM for a high-gain DC-DC stage, offers a solution to complexity in grid current control using feedback linearization, and illustrates a comprehensive control scheme for solar micro inverters.

Texas Instruments
Dallas, TX.
(972) 995-2011