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XMC Module Family Features User-Programmable FPGA

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Two Switched Mezzanine Card (XMC) compatible modules provide a user-programmable FPGA Xilinx XC6SLX45T-2 or Xilinx XC6SLX100T-2 Spartan6 FPGA. The TXMC633 and TXMC635 from TEWS Technologies are designed for industrial, COTS, and transportation applications, where specialized I/O or long-term availability is required. They provide a number of advantages including a customizable interface for unique customer applications and a FPGA-based design for long-term product lifecycle management.

The TXMC633 module versions are available with  64 ESD-protected TTL lines or 32 differential I/O with EIA 422 / EIA 485 compatible, ESD-protected line transceivers or 32 TTL I/O and 16 differential I/O with Multipoint-LVDS Transceiver.  The TXMC635 module features 48 TTL I/O, 8 channels single-ended 16 bit analog output with up to ±10.8V output voltage range, and 32 single ended or 16 differential 16 bit analog inputs with full-scale input voltage range of up to ±24.576V.

For customer-specific I/O extension or inter-board communication, the TXMC633 and TXMC635 provides 64 FPGA I/O lines on P14 and 3 FPGA Multi-Gigabit-Transceiver on P16. P14 I/O lines could be configured as 64 single ended LVCMOS33 or as 32 differential LVDS33 interface.

The User FPGA is connected to a 128 Mbytes, 16 bit wide DDR3 SDRAM. The SDRAM-interface uses a hardwired internal Memory Controller Block of the Spartan-6. The User FPGA is configured by a platform SPI flash or via PCIe download. The flash device is in-system programmable.  An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design (using Xilinx “ChipScope”).

User applications for the modules with XC6SLX45T-2 FPGA can be developed using the design software ISE Project Navigator (ISE) and Embedded Development Kit (EDK). IDE versions are 14.7. Licenses for both design tools are required. TEWS offers a well-documented basic FPGA Example Application design. It includes an .ucf file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the modules. It implements local bus interface to local bridge device, register mapping, DDR3 memory access and basic I/O. It comes as a Xilinx ISE project with source code and as a ready-to-download bit stream.

TEWS Technologies, Reno, NV
(775) 850-5830. www.tews.com